| Age | Commit message (Expand) | Author |
|---|---|---|
| 13 hours | Fix cascading gate: exempt layer 0 from disconnection checkHEADmain | YurenHao0426 |
| 15 hours | Fix NLL double-shift bug and head weight init | YurenHao0426 |
| 16 hours | Fix init state: add logit_bias so A≈1 at init (dense connectivity) | YurenHao0426 |
| 17 hours | Initial implementation: DAGFormer Phase 1 | YurenHao0426 |
