ept.git/hw_sim/cell_v0.py, branch master

ept.git/hw_sim/cell_v0.py, branch master Unnamed repository; edit this file 'description' to name the repository. hw_sim: circuit-as-code workflow stood up (PySpice/ngspice/skidl); cell_v0 — 64-branch settle 1.14us (<=3us gate PASS), two-phase offset rejection x376; sync_wandb follow mode 2026-07-17T20:29:13+00:00 Yuren Hao yurenh2@illinois.edu 2026-07-17T20:29:13+00:00 8470a592dca83fd54f49e88c7352429e5bb0d315 Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_014FAPDWQ49M5Ye3NpTndTpn

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_014FAPDWQ49M5Ye3NpTndTpn