TinyEP hostile audit archived: DEAD per own claim class, SURVIVES-DEGRADED rescoped; portable gold = tied-KV DenseAM energy + same-cell bidirectional access

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_014FAPDWQ49M5Ye3NpTndTpn

3 files changed, 450 insertions, 0 deletions

diff --git a/TINYSTORIES_ANALOG_LM_MVP.md b/TINYSTORIES_ANALOG_LM_MVP.md
new file mode 100644
index 0000000..243df53
--- /dev/null
+++ b/TINYSTORIES_ANALOG_LM_MVP.md
@@ -0,0 +1,345 @@
+# TinyStories analogue language-model MVP
+
+**Revised scope, 2026-07-13**
+
+This document replaces the earlier one-edge learning-tile proposal. The target here is an actual, end-to-end autoregressive language model trained on TinyStories: it accepts a text prompt, maintains context, chooses successive characters, and generates a story. The proposed runtime contains no processor, FPGA, ADC, DAC, digital weight memory, or free-running clock.
+
+The lowest-cost credible route is **not** to reproduce an OLMo2/GPT block. It is to train a compact recurrent student in software, freeze and physically encode its weights, and execute the complete autoregressive loop in analogue hardware.
+
+## 1. Exact claim
+
+Recommended paper/demo claim:
+
+> A self-timed analogue recurrent language model trained on TinyStories, using continuous-valued physical state and passive weight storage, which generates text autoregressively without a processor, data converters, or a periodic clock in the inference loop.
+
+This is a full language model, but the base model is trained offline. It is not a claim of fully analogue pretraining.
+
+A second, higher-risk configuration can train a low-rank readout in situ. That makes all *adaptive* parameters analogue, but the recurrent reservoir/backbone remains fixed.
+
+## 2. Why the original hardware map is the wrong MVP
+
+The existing map keeps an OLMo2-standard Transformer block and then purchases hardware to reproduce every consequence of that choice:
+
+- token lookup and a vocabulary-sized head;
+- Q/K/V projections and causal attention memory;
+- RoPE;
+- QK normalization and RMSNorm;
+- exponential normalization/softmax;
+- gated MLP/SwiGLU;
+- transpose reads for feedback;
+- FPGA sequencing;
+- DAC and ADC boundaries;
+- digitally managed weight programming and optimization.
+
+That is an accelerator integration programme. It is not the minimum hardware needed to demonstrate a TinyStories LM.
+
+The TinyStories paper used GPT-Neo, a context length of 512, a local-attention window of 256, and the 10,000 most common GPT-Neo tokens. Even at hidden width 64, the input embedding alone therefore contains 640,000 weights. The paper also reports that the 1M/width-64 model is weak and that story consistency begins to emerge when width rises from 64 to 128. Preserving the Transformer architecture therefore commits the hardware to approximately one million or more physical weights before analogue attention is addressed.
+
+For analogue hardware, the decisive reductions are:
+
+1. use a small character alphabet instead of a 10,000-token BPE vocabulary;
+2. compress the past into a fixed-size recurrent state instead of retaining a token-by-token attention context;
+3. tie the transition weights across every generated character;
+4. factor dense matrices into low-rank matrices;
+5. use passive, fixed, low-precision weights rather than a programmable CIM evaluation platform;
+6. use winner-take-all selection instead of implementing softmax at inference;
+7. use completion-triggered handshaking instead of a periodic clock.
+
+## 3. Recommended model: `A-Tiny-256`
+
+### 3.1 Tokenization
+
+Normalize TinyStories to a 64-symbol alphabet:
+
+- 26 lowercase letters;
+- 10 digits;
+- space, newline, apostrophe and quotation marks;
+- common punctuation;
+- beginning/end/unknown/control symbols.
+
+Case folding is a deliberate hardware trade. A 96-symbol case-preserving version is possible with a modest increase in the output and input matrices.
+
+Recent recurrent-model research has already used ASCII character-level TinyStories with a 256-symbol vocabulary, so character-level TinyStories is a defensible benchmark rather than a different task in disguise.
+
+### 3.2 State and transition
+
+Use a 256-dimensional continuous state and rank 48 factors:
+
+\[
+ u_t = \tanh(Bh_t + Ex_t + b_u),
+\]
+
+\[
+ c_t = \tanh(Au_t + d\odot h_t + b_c),
+\]
+
+\[
+ h_{t+1} = (1-\alpha)h_t + \alpha c_t,
+\]
+
+\[
+ q_t = Rh_{t+1}, \qquad \ell_t = Sq_t+b_o.
+\]
+
+Here:
+
+- \(x_t\) is a one-of-64 character signal;
+- \(h_t\in\mathbb{R}^{256}\) is the compressed story state;
+- \(u_t,q_t\in\mathbb{R}^{48}\);
+- \(\ell_t\in\mathbb{R}^{64}\) are character scores;
+- \(\alpha\) is a fixed per-group or per-channel leak implemented by conductance ratios, not a multiplier.
+
+Approximate parameter count, excluding biases:
+
+| Matrix | Shape | Weights |
+|---|---:|---:|
+| State compression `B` | 48 × 256 | 12,288 |
+| Character input `E` | 48 × 64 | 3,072 |
+| State expansion `A` | 256 × 48 | 12,288 |
+| Diagonal recurrence `d` | 256 | 256 |
+| Readout compression `R` | 48 × 256 | 12,288 |
+| Character head `S` | 64 × 48 | 3,072 |
+| **Total** |  | **43,264** |
+
+Quantization-aware training should target at least 45–60% exact zeros, leaving roughly 17,000–24,000 populated passive connections. The recurrent core can use ternary weights; input and output matrices should initially use five levels `{-2,-1,0,+1,+2}` because boundary matrices are generally more sensitive.
+
+### 3.3 Why this model rather than a GRU
+
+A full GRU requires three large recurrent projections plus sigmoid gates and hundreds of analogue multipliers. The proposed transition needs one low-rank nonlinear update and obtains its memory from residual/leaky state dynamics.
+
+A 2026 recurrent-pretraining study evaluated character-level TinyStories and found that nonlinear fixed-memory RNN performance improved smoothly with memory size and model scale. It also showed that teacher-derived memory targets can avoid long unrolled credit paths. This supports training a hardware-friendly recurrent student rather than forcing attention into the board.
+
+The model still requires digital pre-validation. No published result establishes that exactly 256 states and rank 48 will meet the desired story-quality threshold. The board should not be fabricated until the hardware-aware digital twin produces acceptable free-running completions.
+
+## 4. Training and compression pipeline
+
+Training is done off-board. Runtime is analogue.
+
+### Stage 1 — character-level teacher
+
+Train or reuse a competent character-level TinyStories Transformer/sequence teacher. Use a teacher with clearly better generation than the TinyStories 1M baseline; the original paper’s examples indicate that 8.3M-class models are a safer quality source than the 1M model.
+
+### Stage 2 — recurrent state distillation
+
+Train `A-Tiny-256` using:
+
+- next-character cross-entropy;
+- soft-logit distillation from the teacher;
+- one-step memory/state targets so the recurrent transition learns a Markovian compressed state;
+- free-running rollout fine-tuning to reduce accumulated drift.
+
+### Stage 3 — hardware-aware quantization
+
+Train with the actual physical constraints:
+
+- core weights ternary;
+- input/output weights five-level;
+- grouped matrix gains rather than individual row calibration;
+- activation saturation;
+- resistor mismatch;
+- amplifier offset and finite gain;
+- switch charge injection;
+- state-capacitor leakage;
+- additive and multiplicative noise;
+- asynchronous settling tolerance.
+
+Do not quantize a completed floating-point model as an afterthought. Train with the discrete weight set in the forward pass.
+
+### Stage 4 — fabrication export
+
+The export script produces:
+
+- a sparse crosspoint list for each passive matrix;
+- resistor value and polarity at every nonzero crosspoint;
+- matrix-level/group-level gain resistors;
+- a SPICE netlist with measured component distributions;
+- PCB pick-and-place files;
+- a golden teacher-forced voltage trace for bring-up.
+
+## 5. Analogue hardware map
+
+### 5.1 Passive weight ROM
+
+Each matrix is a signed passive summing network. State and latent signals are differential. At each nonzero crosspoint:
+
+- sign chooses the positive or negative source rail;
+- magnitude chooses one of two resistor values;
+- zero omits the component.
+
+This is a physical analogue ROM. It is not programmable during runtime, but it avoids the cost and peripheral complexity of memristor/SRAM-CIM evaluation hardware.
+
+Use plug-in matrix cards so a new trained model requires replacing only passive cards, not the state and control boards.
+
+### 5.2 State
+
+Use two 256-channel capacitor banks:
+
+- bank A holds `h_t` while bank B acquires `h_{t+1}`;
+- after analogue completion detection, the banks exchange roles;
+- low-input-bias buffers isolate the capacitors;
+- a manual freeze input stops generation without refreshing or digitizing the state.
+
+Two banks make the physical update correspond closely to the trained discrete recurrence. A later continuous-time single-bank version can be investigated after the model works.
+
+### 5.3 Nonlinearities
+
+Implement the two tanh-like banks with saturating differential or diode-feedback amplifiers:
+
+- 48 channels for `u_t`;
+- 256 channels for `c_t`.
+
+Exact mathematical tanh is unnecessary. The measured transfer curve is inserted into hardware-aware training.
+
+### 5.4 Residual/leak update
+
+Implement
+
+\[
+ h_{t+1}=(1-\alpha)h_t+\alpha c_t
+\]
+
+with resistor ratios and capacitor charging. No Gilbert multiplier is needed. Use 8–16 shared leak groups initially; per-channel leak values can be added only if digital ablations show a material gain.
+
+### 5.5 Character selection
+
+A 64-way current-mode winner-take-all network selects the next character directly from the logits. Softmax is unnecessary for deterministic generation. The TinyStories paper itself reports many sample completions at zero temperature.
+
+For diverse generation, add a controllable analogue noise voltage to the logits before winner-take-all. This is not exact categorical softmax sampling, but it is adequate for a research comparison between deterministic and noisy generation.
+
+### 5.6 Prompt and output
+
+- Prompt entry: a passive keyboard/diode matrix produces one-of-64 character lines. Each key event advances the state through the same self-timed transition used during generation.
+- Generation: the winner line is fed directly back as the next one-of-64 input.
+- Visible output: 64 labelled LEDs are sufficient for a strict no-digital demo. A logic analyser or computer may record the winner lines for plots, provided it is electrically outside the feedback loop.
+
+## 6. No-clock operation
+
+A language model necessarily emits discrete characters, so some event boundary is unavoidable. “No clock” should mean **no oscillator and no periodic global timing reference**, not “no bistable state anywhere.”
+
+The controller is completion-driven:
+
+1. source state and current character are held;
+2. the destination state capacitors move toward their new values;
+3. an aggregate settling circuit monitors total state-update current or slew;
+4. the winner-take-all margin must remain stable for an RC qualification interval;
+5. a comparator/latch emits one transition event;
+6. the token latch and state-bank roles exchange;
+7. the next analogue computation begins immediately.
+
+The character rate therefore changes with physical settling time. There is no free-running clock, phase counter, or firmware scheduler.
+
+The most accurate wording is **self-timed analogue datapath with asynchronous event control**. Calling it a purely continuous analogue system would be misleading because characters are discrete symbols.
+
+## 7. Estimated bill of materials
+
+These are engineering estimates for one assembled research system, excluding ordinary laboratory instruments and software-training compute. PCB assembly quotes will dominate the uncertainty.
+
+### Recommended `A-Tiny-256`
+
+| Category | Indicative implementation | Estimate |
+|---|---|---:|
+| Passive matrix cards | 4–5 PCBs; approximately 17k–24k populated 0402/0201 resistors after pruning | $220–450 |
+| Summing, buffering and saturation | approximately 200–350 low-cost quad op-amp packages, mixed LM324-class and TLV9004-class | $120–260 |
+| State banks and switches | 512 capacitors, low-leakage buffers, approximately 100–150 quad analogue-switch packages | $70–160 |
+| WTA and completion detector | comparator/WTA cells, latches, RC qualification, noise option | $30–90 |
+| Power, connectors, backplane and prompt panel | split or virtual-ground supply, headers, LEDs, keyboard matrix | $70–160 |
+| Rework and component tolerance margin | spare boards/components | $100–220 |
+| **Expected research build** |  | **$610–1,340** |
+
+A conservative grant/BOM line should be **$1,500**, not $5,000–$20,000.
+
+### Scale options
+
+| Version | State/rank | Approx. weights | Purpose | Estimated build |
+|---|---:|---:|---|---:|
+| `A-Tiny-128` | 128 / 24 | 12,416 | full-loop electrical prototype; language quality may be weak | $280–600 |
+| **`A-Tiny-256`** | **256 / 48** | **43,264** | recommended end-to-end LM MVP | **$610–1,340** |
+| `A-Tiny-512` | 512 / 64 | 107,008 | quality contingency after digital validation | $1,400–2,800 |
+
+Relative to the realistic $10,000–$20,000 part of the original estimate, the recommended build is roughly an order of magnitude cheaper while including the entire autoregressive loop rather than one Transformer block.
+
+## 8. What to delete from the existing component map
+
+| Existing item | TinyStories analogue MVP replacement |
+|---|---|
+| 10k-token embedding lookup + DAC | 64-line character input and passive `E` matrix |
+| RoPE mixers/DDS | delete |
+| Q/K/V and attention projection crossbars | fixed-memory recurrent transition |
+| QK normalization | delete |
+| causal softmax | delete; 64-way WTA at output only |
+| causal KV/context memory | 256 analogue state voltages |
+| SwiGLU | two saturating-amplifier banks |
+| RMSNorm banks | bounded recurrent state and matrix-level gains |
+| bidirectional transpose access | delete for inference MVP |
+| ADC + digital LM head | passive `R/S` matrices + analogue WTA |
+| FPGA/phase sequencer | completion detector + asynchronous latch |
+| programmable CIM evaluation board | plug-in passive resistor ROM cards |
+| digital optimizer/write-pulse system | offline training and fixed weight export |
+
+## 9. Optional in-situ analogue-learning variant
+
+If learning in hardware is required for the first paper, use a reservoir/readout configuration rather than trying to adapt all 43,000 weights.
+
+Recommended limit:
+
+- fixed recurrent backbone and fixed `R` projection;
+- 48 latent readout features;
+- 64 outputs;
+- 3,072 adaptive readout weights;
+- local sign-LMS or analogue delta updates under teacher forcing.
+
+This is still an actual autoregressive TinyStories language model. All trainable parameters are analogue, but the base recurrent dynamics are fixed. Expected additional cost is approximately $350–800, with substantial layout and drift risk.
+
+A full 43,000-weight adaptive board is not a low-cost COTS project. Commercial memristor teaching hardware illustrates the mismatch: a current $800 discovery board exposes only a 1×16 device array, and a $2,000 crossbar product exposes at most a 32×32 array and is listed as sold out. Scaling such kits to a language model is economically and architecturally irrational.
+
+## 10. Fabrication gates
+
+Do not order the full board until all of the following pass in the digital twin:
+
+1. `A-Tiny-256` generates multi-sentence, 200–500-character TinyStories completions from held-out prompts.
+2. It maintains at least basic entity and topic continuity better than a character n-gram baseline.
+3. Ternary/five-level quantization causes an acceptable degradation in held-out loss and human/GPT story grading.
+4. Free-running rollouts do not collapse into short loops under the planned noise and mismatch distributions.
+5. A SPICE/macromodel simulation reproduces the quantized model’s top-character choice on representative teacher-forced traces.
+6. The asynchronous controller produces exactly one state/token transition per settled computation over process, voltage and temperature sweeps.
+
+If the 256/48 model misses the language-quality gate, increase state/rank in software first. Do not compensate by adding transformer peripherals to the hardware.
+
+## 11. Experimental programme
+
+The first publishable evaluation should include:
+
+- digital floating-point teacher;
+- quantized digital recurrent student;
+- circuit-macromodel student;
+- physical analogue board;
+- teacher-forced logit correlation and top-1 agreement;
+- free-running divergence length;
+- story grammar, consistency and repetition scores;
+- characters per second and joules per character;
+- supply, temperature and resistor-mismatch sweeps;
+- deterministic WTA versus noisy WTA;
+- state dimension/rank ablation;
+- 128-state electrical prototype versus 256-state final board.
+
+## 12. Claims not to make
+
+Do not claim:
+
+- OLMo2 equivalence;
+- a Transformer implementation;
+- exact softmax sampling;
+- fully analogue pretraining of all weights;
+- a mathematically clock-free continuous system;
+- TinyStories-2.5M-equivalent quality before measurements.
+
+The defensible contribution is stronger and cleaner: **a complete, self-timed analogue language-model inference loop on TinyStories**, with a cost and component count appropriate to an academic laboratory.
+
+## References
+
+- Ronen Eldan and Yuanzhi Li, “TinyStories: How Small Can Language Models Be and Still Speak Coherent English?”, 2023. https://arxiv.org/abs/2305.07759
+- Akarsh Kumar et al., “Pretraining Recurrent Networks without Recurrence”, 2026. https://arxiv.org/abs/2606.06479
+- Felix Köster and Atsushi Uchida, “Reservoir Computing as a Language Model”, 2026. https://arxiv.org/abs/2507.15779
+- Sam Dillavou et al., “Machine Learning Without a Processor: Emergent Learning in a Nonlinear Electronic Metamaterial”, 2024. https://arxiv.org/abs/2311.00537
+- Knowm, Memristor Discovery and crossbar product pages. https://knowm.com/
+- Texas Instruments, TLV9004 and CD4066B product documentation. https://www.ti.com/
diff --git a/docs/hardware/MSCALE_COST_ALGEBRA_SEARCH_SPEC.md b/docs/hardware/MSCALE_COST_ALGEBRA_SEARCH_SPEC.md
new file mode 100644
index 0000000..658075f
--- /dev/null
+++ b/docs/hardware/MSCALE_COST_ALGEBRA_SEARCH_SPEC.md
@@ -0,0 +1,52 @@
+# M-SCALE EP TRAINER — COST ALGEBRA + SEARCH SPEC (2026-07-13)
+
+TARGET OBJECT: a TinyStories-class LM with M = 1–5M ANALOG-TRAINED weights, transformer-shaped per COMPONENT_HW_MAP.md (crossbar MVMs, divisive norms, entropic softmax, gated MLP; token embedding + LM head digital at the boundary), TRAINED end-to-end by Equilibrium Propagation two-phase local updates on the physical substrate. Inference-only hardware scores ZERO here. The $150–260 rung-A tile (CLOCKLESS_ANALOG_MVP_PLAN.md) is NOT the subject.
+NULL HYPOTHESIS (what you must beat): HW_FIRST_PRINCIPLES_SEARCH.md rung-C verdict — "the M-scale training claim lives ONLY on partner CIM silicon (UIUC), conditional on two unverified die modes; no purchasable substrate survives rung C." You win by producing a purchasable or self-owned path to grade ≥B (defined in §2.3) at M scale in a lower budget band, or any credible grade-A(M) path at any band. Doctrine: COTS / eval boards / FPGA / partner silicon — never tapeout.
+Source tags [D][F][C][M][H][A][P][X] = the audited numbers in HW_FIRST_PRINCIPLES_SEARCH.md (2026-07-13). New prices below were live-checked 2026-07-13 (DigiKey/Mouser); treat every single-quantity price as ±10% and re-verify at order time [D §6.5].
+
+## 1. COST ALGEBRA
+TotalCost = N_phys · c_cell + C_periphery + C_integration,  with  N_phys = M / R.
+- N_phys = physical trainable cells. R = time-multiplex reuse factor: one physical tile/row/block serves R logical weight tiles; weights stream between physical cells and a backing store between residencies.
+- c_cell = all-in cost per physical trainable cell (device + its share of the local update/contrast circuit + trim). Measured anchors: discrete twin edge $19–33/cell (8-edge board $150–260 [D]); digipot edge $19–31/cell all-in, $0.45/wiper raw (MCP4451-103E/ST quad, $1.80 DigiKey [H]); UIUC 28nm SRAM-CIM bank $1.1–1.9k BOM for a block-scale array [P] → c_cell ≈ $10⁻³–10⁻² only when integrated.
+- C_periphery = DAC/ADC boundary, nudge injectors (OTA class), norm/softmax cells, θ-readout chain, backing store + its bus, harness host (PYNQ-Z2 $178.44 LCSC [P]). Backing-store SILICON is cheap: 5M weights × 8b = 40 Mbit ≈ ten 4-Mbit FRAMs (CY15B104QN-50SXIT $12.74, 1,732 in stock DigiKey; MB85RS4MTYPF $17.38) ≈ $130–175, or pennies as SRAM/DDR on the host. The real periphery cost is (a) the RESTORE PATH — DACs or program-pulse drivers running at the §2.1 bandwidth — and (b) null/offset engineering: per-edge trims do not scale to 10⁵–10⁶ cells; budget auto-zero front-ends and architectural zeroing ([D]: the zero-contrast null, not the BOM, is the critical path).
+- C_integration = boards, gateware, bring-up at LOADED labor rates + one respin. Precedent: UIUC $1.1–1.9k BOM but $20–40k loaded labor [P]; FPGA harness gateware 1–3 eng-months [X].
+- Feasibility frontier (must be computed per candidate): c_cell ≤ Band / (M/R). Worked at M=2.5M: $3k band, R=6 (one transformer block resident) → N_phys=4.2·10⁵ → c_cell ≤ $0.0072 → integrated cells only; R=2,500 (N_phys=1,000, one 32×32 tile) → c_cell ≤ $3 → discrete/digipot enters, but the §2 swap wall must then be paid. Report your (R, N_phys, c_cell, BW_load) point explicitly.
+
+## 2. WHAT BOUNDS R FROM ABOVE
+Reference workload for all arithmetic: M=2.5M (d=192, L=6 blocks, ≈12d² ≈ 4.4·10⁵ weights/block), b=8 stored bits (≥7 effective, §3), batch·seq = 2048 tokens/step, N_steps = 4.9·10⁴ (100M tokens) or 4.9·10⁵ (1B tokens), nudged relaxation K=3 (map B.12). Scale to your M.
+2.1 WEIGHT-SWAP BANDWIDTH AND TIME.
+- Activation-buffered regime (each tile loaded once per pass, the whole batch streamed through it while resident): T_swap/step = 2·M·b / BW_load — note this is R-INDEPENDENT; bandwidth, not R, is the wall, R only divides cost. 2Mb = 40 Mbit/step: at 50 Mb/s (SPI/QSPI class) → 0.8 s/step → ≈11 h of pure swap per 100M-token run (fine; ×10 at 1B = 4.6 d); at I²C 400 kb/s → 100 s/step → ≈57 d (DEAD). The factor 2 = one forward-sweep load + one reverse-order nudged/feedback-sweep load per step.
+- Unbuffered / sub-block-streamed regime (weights restream per token): traffic = 2·N_tok·M·b = 4 Pbit per 100M-token run → needs ≥10 Gb/s sustained INTO ANALOG CELLS to finish in ~5 d. A digital DDR bus does this trivially; a DAC-per-column restore path at that rate is where the money goes — price it, per channel, at the required rate (no audited anchor exists; do NOT hand-wave it).
+- Buffering is not free of claims: batching a resident tile requires holding activations (and partial sums, if the tile is smaller than a matrix) at block/tile boundaries — see 2.3 last bullet.
+2.2 SWAP ENERGY AND CELL ENDURANCE. E_swap = 2·R·N_steps·N_phys·b·e_write = 2·N_steps·M·b·e_write. SRAM/register writes ~pJ/b → joules per run, free. If the PHYSICAL cell is reprogrammed each residency, each cell sees 2·R·N_steps writes/run: at R=6 → 5.9·10⁵ (100M tok) to 5.9·10⁶ (1B). Qualified endurance: flash 10⁴–10⁵ DEAD; Knowm memristor qualified 10⁴ DEAD [M]; RRAM ~10⁶ MARGINAL at 100M / DEAD at 1B, ~10⁸ OK; PCM ~10⁷–10⁹ OK-ish; SRAM / capacitor / digipot-volatile-register unlimited. Verify endurance AND write time per part — [C] precedent: 0.7–4·10⁷ pulses/cell = months–years of write time killed all COTS CIM. Program-pulse energy (nJ–µJ) × 2·N_steps·M·b can also dominate the power budget — show it.
+2.3 BACKING-STORE TECHNOLOGY → CLAIM GRADE AT M SCALE. "R6 sentence" = the public claim the build licenses. If a weight lives digitally between uses, the rung-A clockless sentence is dead by construction; what survives is graded:
+- GRADE A(M): no digital representation of any weight or gradient exists at any time during training. Backing store analog (held charge, analog floating gate) with analog transport, or R small enough to be weight-stationary. Digital allowed only at the token/label boundary (map A.1/A.10) and for phase sequencing (the M-scale concession vs rung-A). Reality check owed by any A(M) claimant: LF398-class S/H is $1.91/cell (LF398MX/NOPB, DigiKey — DEAD ×M as discrete) and droops 5 mV/min at 1 µF best-case ≈ ½ LSB @ 8b/5V FS in ~2 min → an M-cell analog store is a refresh machine; show the refresh loop closes without digitizing.
+- GRADE B+(M): the GRADIENT exists only as a physical two-phase contrast, read locally at the tile (analog outer-product / contrast cell); weights are digitized between residencies at a width ≤ the cell's effective bits — no higher-precision digital shadow. Sentence: "an M-weight transformer LM trained by physical EP dynamics, with declared digital weight logistics."
+- GRADE B−(M): as B+ plus a wider digital accumulator (16–32b shadow, ≥7b restore) — the standing map-B.16 doctrine, and the known fix for 1-LSB-quantized updates stalling near convergence (step-0 channel [H][X]). Sentence: "physical EP gradient estimator; digital weight state." Referee risk: "digital training with an analog gradient estimator" — pre-register the wording before building.
+- GRADE C(M): the nudged/feedback phase is computed digitally from digitized activations, or the analog part does forward MACs only ("analog matmul + digital loop" — the forbidden claim [C]). AUTO-REJECT: inference hardware in disguise.
+- Two EP-critical hardware modes gate every candidate (the generalized UIUC die-mode questions [P]): (i) transpose/bidirectional MVM path for Jᵀ feedback; (ii) local per-tile analog outer-product or two-phase contrast readout. Missing either, with no analog workaround → grade C, reject. Dual-copy W/Wᵀ workarounds inherit the measured 0.3–1.5% drifting mismatch channel [F][C][P][A] — fault-inject before trusting.
+- Mid-network state handling is itself a claim item: cascade single-sided θ-read (free-phase ∂E/∂θ ≡ 0, map B.13) still needs free-phase activations present at nudged time; held-analog (report the droop ledger) vs digitized (ADC inside the loop → B at best). Same fork for partial sums in sub-block tiling.
+2.4 SETTLE TIME PER PHASE. T_settle_total ≈ N_tok · L · (1+K) · t_settle (≈4 settle events/token/block; K=3). At 100M tok, L=6: t_settle 10 µs → 6.7 h; 100 µs → 2.8 d; 1 ms → 28 d MARGINAL. At 1B tok: 10 µs → 2.8 d; 100 µs → 28 d MARGINAL; 1 ms → 280 d DEAD. Classes: discrete RC boards 10 µs–1 ms [D-class]; digipot settle math was off ~10× in the proposal — recompute, don't quote [H]; CIM ns–µs [C][P].
+2.5 WALL-CLOCK GATE. T_train ≈ T_settle_total + N_steps·(2Mb/BW_load) + T_update_writes + harness overhead (measure it; USB/host round-trips killed proposals before [X]). One full TinyStories run (state your token count in 100M–1B): ≤14 d PASS; 14–60 d MARGINAL; >60 d DEAD (the [C] kill rule).
+
+## 3. TOLERANCE FLOOR (measured, cascade E-tier, 42.7M-weight reference — binding at 1–5M until re-measured; from COMPONENT_HW_MAP.md)
+- Weight precision: ≥7-bit EFFECTIVE after mismatch/INL/drift. Measured: wq8 FREE (ΔCE +0.004, cos_clean 0.96); wq6 MARGINAL (+0.051, 0.81); wq4 DEAD (+2.23). Precedent trap: digipots are 8b by construction but wiper INL → 5–6 effective bits raw; per-edge cal required [H]. "Effective bits under drift/limit-cycle" must be measured, not datasheet-copied (the unanswered CLLN question [P]).
+- Forward path: additive state noise ≤1% (σ=1e-2) FREE; device mismatch ~3% FREE (10% MARGINAL: +0.042, 0.78 on norms); multiplier/gate gain error ≤10% FREE; RoPE phase error 0.03 rad (~2°) FREE.
+- Error channel (feedback/nudged path): ≤10% noise FREE. The β-floor/ramp schedule is the SNR lever; nudge amplitude is free against MULTIPLICATIVE noise (r-indifference) — ADDITIVE readout noise is what kills. ADC bits at the θ-read buy the same margin as β.
+- Every candidate maps its own measured/datasheet numbers onto these four floors line by line. Step-0 fault channels remain purchase gates: replica asymmetry 2/5/10%, Wᵀ mismatch 0.3/1.5%, 1-LSB updates @7/8/10b [D][F][H][P][X]; ADD for M scale: activation-hold droop/quantization channel (2.3 last bullet).
+
+## 4. BUDGET BANDS (all-in: parts + boards + backing store + restore path + null engineering + loaded integration labor)
+- SELF-FUNDED ≤ $3k | ADVISOR/PARTNER-SHAPED ≤ $30k | GRANT-SHAPED ≤ $150k.
+- THE PRIZE: push an M-scale TRAINING machine into the lowest possible band. Prior art to beat: the only surviving M-scale line was $20–40k loaded, grade-B-CONDITIONAL, partner-gated, 1–3 months [P]. Beating ANY coordinate counts: lower band, higher claim grade, purchasable-today instead of partner-gated, or faster wall-clock — but report all coordinates honestly.
+
+## 5. SCORING RUBRIC — report ALL six per candidate; kill rules at bottom
+1. AUDITED $ PER BAND: itemized BOM with live distributor price + stock + date per line; restore-path and null-engineering lines REQUIRED; labor at loaded rates → assign band. An uncosted critical path = FAIL (the [D] null-engineering lesson: +$25–80/board at 8 edges, unknown and probably architectural at 10⁵ cells).
+2. CLAIM GRADE AT M SCALE: A / B+ / B− / C per §2.3, with the exact R6-style sentence the build licenses, and mode-(i)/(ii) evidence from a datasheet, die document, or vendor simulator — not marketing copy.
+3. R ACHIEVED: the tuple (R, N_phys, c_cell, BW_load, regime = buffered|streamed), placed on the §1 frontier, plus a one-line statement of WHICH §2 bound binds R for this candidate (bandwidth / endurance / buffer-claim / cost).
+4. WALL-CLOCK TO TRAIN TINYSTORIES ONCE: full §2.4–2.5 arithmetic at 100M AND 1B tokens with t_settle measured-or-datasheet and the swap term shown → PASS / MARGINAL / DEAD.
+5. TIME-TO-FIRST-RESULT: weeks to (a) first measured two-phase θ-read on the real substrate, (b) first full M-scale training run. NDA, waitlist, restock, and tool-archaeology time COUNT ([C]: 6–18 mo NDA; [F]: 1–2 mo tool archaeology; [M]: unbounded restock).
+6. SUPPLY-CHAIN FRAGILITY: single-source? stock TODAY (dated screenshot or quote)? manufacturer lifecycle page, not distributor rumor (the LM13700 three-contradictory-readings fiasco [D][P][X]); precedents: Knowm all SKUs sold out [M], Okika 29 boards on Earth [F]. Name a second source or score RED.
+KILL RULES: grade C at M scale → DEAD. Wall-clock >60 d/run → DEAD. Cell endurance < 2·R·N_steps writes (when cells are rewritten) → DEAD. Any §3 floor missed without a costed mitigation → DEAD. Any capacity claim >10× the largest independently demonstrated array on that substrate requires compile/measurement evidence, not a ratio ([F]'s fabricated 600k× lesson).
+RETURN FORMAT: one table row per candidate carrying scores 1–6, then ≤10 lines of dissent: what single new fact would resurrect this candidate if killed (the [M]/[F] re-look discipline).
+
+Sources: repo audits = HW_FIRST_PRINCIPLES_SEARCH.md + COMPONENT_HW_MAP.md + CLOCKLESS_ANALOG_MVP_PLAN.md (all 2026-07-13/-11). Live prices 2026-07-13: LF398MX/NOPB $1.91 + 5 mV/min droop (digikey.com/en/products/detail/texas-instruments/LF398-MDC/7312649, analog.com lt0198 datasheet); FRAM CY15B104QN-50SXIT $12.74 / 1,732 stock, MB85RS4MTYPF $17.38 (digikey.com/en/products/detail/kaga-fei-america-inc/MB85RS4MTPF-G-JNERE2/9748469, /ramxeed/MB85RS4MTYPF-G-BCERE1/13539951); MCP4451 $1.80, PYNQ-Z2 $178.44, ALD1106/AD633/LM13700 prices = [H][P][D] audits.
diff --git a/docs/hardware/TINYEP_HOSTILE_AUDIT.md b/docs/hardware/TINYEP_HOSTILE_AUDIT.md
new file mode 100644
index 0000000..96f896c
--- /dev/null
+++ b/docs/hardware/TINYEP_HOSTILE_AUDIT.md
@@ -0,0 +1,53 @@
+# HOSTILE AUDIT — TinyEP-256-R32 (TINYSTORIES_EQPROP_ANALOG_TRAINER_MVP.md), 2026-07-13
+
+Reviewer stance: mixed-signal tape-out + bench + referee. Baselines: MSCALE_SUPPLY_CHAIN_SEARCH.md (M-study), HW_FIRST_PRINCIPLES_SEARCH.md ([D]/[X]/[H] audits).
+
+## (a) PLACEMENT — evades the residency theorem, walks into the retention wall
+
+- **Residency theorem: genuinely evaded.** The theorem's antecedent (model > physical array → sub-block residency → digitized inter-block activations → B/B− ceiling) does not hold: all 37k weights are resident, R=1, no streaming, no tile edge to digitize. Reuse-forced volatility is also evaded — cells absorb no reload writes, only analog update currents (no endurance arithmetic).
+- **But the theorem has a corollary the proposal never confronts: full residency on volatile cells trades digitization for droop.** 2N7002-class access FETs leak 1–100 nA typ at datasheet spec (~10 pA–10 nA derated at ~1 V cell bias); on 10–100 nF that is 1 LSB (8 mV @ 8-bit, ±1 V span) per **~0.1–100 s per cell**, consistent with [D]'s measured CD4066 line (1 LSB in 3–6 min on ≥4.7 µF ⇒ 4–8 s scaled to 100 nF). Effective per-weight decay τ ≈ **minutes–hours**, with 10–100× per-cell spread. Training updates shrink toward zero near convergence; droop doesn't. The machine is the M-study's "refresh machine" with training as the refresh — a droop-limited loss floor, the LF398 arithmetic transposed from S/H to the weight bank itself. "Leak = weight decay" is a euphemism: mismatched per-cell λ is a random decay field, not a regularizer.
+- **≤$3k flagship-enabler? No.** It escapes the M-band's walls by shrinking the object, but it does not land in the band (see (c): honest parts $5–12k), and the object it shrinks to is no longer the thing the band's flagship sentence needs (see (d)/(e)). The M-study's ruling — ≤$3k buys metrology, not a trainer — stands.
+
+## (b) PHYSICS — the energy is real; the scanner spends EP's one advantage
+
+- **Conservative construction: PASS on paper, and it is the proposal's best idea.** Tied-K/V softmax attention over clamped context embeddings is exactly the modern-Hopfield/DenseAM energy (∂E/∂z of −logsumexp = softmax-weighted sum of the same vectors); the rank-32 factors as physical bilinear layers, the 512-unit rectified memory, tied embed/decode, and leak give a legitimate layered energy. Classic EP legal, no transpose circuitry: same-cell forward/transpose access is the analog analogue of T64's word-transpose — **mode (i) exact by construction**, the strongest reciprocity evidence class in either prior study. The p−y nudge current is standard and clean.
+- **Simultaneous settle: broken and replaced, semi-defensibly.** 16–32 shared lanes over 37k weights means the state never relaxes under the full physical energy; it is Gauss-Seidel coordinate descent by scanned analog MACs. For a contractive energy (their leak gate) async relaxation reaches the same fixed point (Bertsekas-Tsitsiklis conditions), and EP only needs the fixed points — so the *gradient theorem* survives, contingent on gate 4. "Both replicas settled before update integration" is enforceable (two residual envelopes AND-ed into a C-element; ± replicas in matched parallel lanes). But EP's selling point — physics does the relaxation in constant time — is forfeited; the machine is a self-timed serial processor whose ALU is analog.
+- **Wall-clock: the kill.** Per-sweep MACs ≈ 131k (attention: 8×256×32 scores + value sums) + ~70k (bilinear banks); context-embedding instantiation is 256×8,192 ≈ **2.1M MACs/example** — which requires either an uncosted ~65k-cell analog hold bank (1.8× the weight array) or recomputation every sweep (5–10× time). Per example: 2 phases × 15–30 sweeps × 200k MACs ÷ 32 lanes × 1–5 µs/slot (LM13700/AD633 GBW floor; T64's own kill line was 7 µs) ≈ **0.1–0.5 s/token floor** (4-way batch broadcast included), 1–2 s realistic. 100M char-tokens = **115–580 days; 500M = 1.6–8 years. DEAD** by the 30-day rule. The only survivable envelope: ≤10–15M tokens at ≤0.25 s/token = 12–30 days, MARGINAL. (T64 does 100M tokens in 9–14 d with 15× the model — digital logistics pipeline the settles; all-analog scanning is slower, not faster.) Add read-disturb: ~80 cell accesses/example × charge injection 1–30 pC ⇒ 0.01–0.3 mV/event on 100 nF; even dummy-switch-cancelled ×10, an accumulating per-example bias competing with a 0.1–1 mV contrast signal [D].
+
+## (c) COSTS — line-by-line correction
+
+| Line | Proposed | Corrected (parts) | Basis |
+|---|---:|---:|---|
+| 37k cells + cards | $650–1,250 | **$1.5–6k** | SC-1M audited c_cell $0.033–0.05 all-in ⇒ $1.2–1.9k floor at cheap caps; but the proposal's own leakage/DA gate forces low-DA dielectric: 100 nF C0G exists only in 1206-class (TDK C3216NP0/Yageo) at ~$0.2–0.5 ⇒ $6–19k in caps alone, vs 10 nF C0G cheap but 10× droop/injection. The fork is unpriced. |
+| 16–32 dual-sign MAC/update lanes | $180–420 | **$1–2.5k + trim labor** | 64 matched four-quadrant multipliers: AD633JRZ $10.97 audited = $700 alone; LM13700M $1.52 route reopens the [D] offset war (±5–50 mV vs 0.1–1 mV contrast) ⇒ per-lane auto-zero front-ends, the [D] unpriced critical path ×37k cells through 32 lanes. SC-1M's functional equivalent (analog product engine) audited at **$8–15k**. |
+| 256-ch softmax bank | $80–220 | $300–800 + cal | V_T mismatch 1 mV = 4% exp error; 256-way matching = trim/selection labor, not parts. |
+| State banks/integrators/detectors | $180–400 | $800–2k **+ $2–5k embedding hold bank (or 5–10× wall-clock)** | 8 replicas × ~800 nodes; the 65k-cell context-memory store is absent from the BOM entirely. |
+| Row/col RMS optimizer + controller | $100–250 | $500–1.2k | ~1,200 envelope-detector + variable-gm cells. |
+| Power/backplane/spares | $200–450 | $300–700 + one respin $200–600 [D] | 4–8 large guarded cards. |
+| Missing lines | — | async address chains $300–800; corpus reader $150–400; **null/cal bench labor (the [D] finding: the money is the null, not the BOM)** | |
+
+**Corrected: parts $5–12k; loaded $25–50k** (M-study accounting). The proposal's $1.4–3.0k is a 3–5× parts and ~15× loaded understatement; the missing money is exactly where SC-1M's budget went — the product engine, the hold/readout periphery, and calibration. Sanity anchor: SC-1M, 49k cells, $40–78k all-in.
+
+## (d) QUALITY RISK — 6× below the published coherence floor, on harder tokens
+
+Eldan-Li's demonstrated range is **1M–35M params on a reduced-vocab word-level tokenizer**; coherent multi-paragraph stories start at ~1M. TinyEP is 164k *effective* (37k physical), char-level — below the paper's floor by ~6× on capacity and on a strictly harder tokenization, before the EP-estimator tax (cos(EP,BPTT) ≈ 0.9 ceiling in this program's own software) and the analog fault stack. Honest forecast: held-out bits/char plausibly beats a 5-gram (n-grams plateau ~1.9–2.2 b/c on TinyStories-simple text; a 164k char model can reach ~1.7–1.9), so **gate 2 as literally written is passable**; completions will show correct spelling and local syntax and zero story coherence. "Readable completions" honestly = readable *words*, not stories. To reach the paper's coherence floor: ~1–3M effective ⇒ rank 128+ and wider memory ⇒ 150–300k physical cells ⇒ the M-band machine ($40–80k) this proposal was built to escape. Rank 64 (328k eff) does not get there either.
+
+## (e) CLAIM — mechanism exceeds the bar, object fails it
+
+- Per the M-study ruling, the minimum object licensing "an LM trained in analog hardware" is D2/B−: both phases physically settled, edge digitization, digitally composed updates — *on a real LM* (T64's pre-registered sentence names a 2.5M transformer). TinyEP is **stronger than D2 on mechanism** (no ADC/DAC/processor anywhere: updates, optimizer state, control all analog — an A-shaped loop) and **weaker on object** (164k-effective char model, below the field's own coherence floor).
+- The M-study's referee kill ("digital training with an analog gradient estimator") does **not** fire — nothing is digital. It is replaced by two new kills: (1) **"not really an LM"** — the referee samples text, reads word salad, and the headline noun dies; (2) **"your self-timed one-hot scanner over 37k weights is a serial processor with an analog ALU — the physics performs no parallel relaxation; what does EP buy?"** Kill (1) is near-certain at flagship if the claim sentence in §9 is kept verbatim.
+- Licensed sentence (defensible, NeurIPS/Nat-Comms hardware track): *"End-to-end in-situ training of an energy-based attention **sequence model** by Equilibrium Propagation in a self-timed switched-analog circuit, with weights, nudges, updates, and optimizer statistics as physical charges; X bits/char vs n-gram baseline, N=37k physical weights."* — "language model" demoted from headline to caveat. Also mandatory citation exposure: Kerjan-Høier-Scellier (2606.03584) already holds EP-transformer territory in software; Yi 2022/Momeni 2023 hold hardware-training precedent; the only unclaimed cell is "attention + fully-analog loop," and that is what the sentence must sit on.
+
+## (f) VERDICT
+
+- **Corrected cost:** parts $5–12k, loaded $25–50k (claimed $1.4–3.0k: rejected).
+- **Corrected wall-clock:** 0.1–0.5 s/token floor ⇒ 100M tokens 115–580 d **DEAD**; feasible envelope ≤10–15M char-tokens in 12–30 d, which further degrades (d).
+- **Grade:** attempted A(37k); expected **B(37k)-contested** (scanner ruling + droop floor); C if the LM noun is retained against word-salad samples.
+- **Survival per its own claim class** ("end-to-end analog-EP TinyStories LM, $1.4–3k"): **DEAD** — cost ×4–15, wall-clock ×10–40, quality 6× under the published floor. **SURVIVES-DEGRADED** as re-scoped: 10M-char budget, mechanism-first sequence-model claim, corrected budget class.
+- **Ladder position:** does not open the ≤$3k band (that band's correct spend remains the M-study's metrology package). Slots *between* the $150–260 grade-A tile (still the correct first physical spend) and T64 ($52–82k, B−, real 2.5M LM) — at roughly SC-1M's price point with a purer mechanism and a weaker object. Its genuinely novel, program-portable assets: the tied-K/V DenseAM energy (conservative attention, no J^T — relevant to the ept software line), and same-cell bidirectional access as analog mode-(i)-by-construction.
+- **Load-bearing gates (of its own 1–7):** **Gate 5** (fault twin — but extended: per-cell random decay τ=0.5–10 h with 10× spread, read charge-injection accumulation, lane offsets vs 0.1–1 mV contrast; this gate decides existence), **Gate 4** (async coordinate-order stability — decides both EP-legality and the sweep count that sets wall-clock), **Gate 2 run at the feasible token budget** (≤10–15M chars, not unlimited — otherwise it gates nothing). Add a missing **Gate 0**: pre-registered wall-clock ledger (slots × slot-time × sweeps × tokens ≤ 30 d) plus a costed design for the 65k-cell context-embedding store. All gates are $0 GPU work and worth running before any board spend; the board is not.
+
+Sources: 2N7002 leakage — Nexperia/Infineon/onsemi datasheets; 100nF C0G 1206 — TDK C3216NP01H104J, Yageo CC1206JKNPO9BN104 (DigiKey); TinyStories arXiv:2305.07759.
+
+---
+*Hostile audit by a single English-only agent against the two prior workflow studies, 2026-07-13.*