TinyEP hostile audit archived: DEAD per own claim class, SURVIVES-DEGRADED rescoped; portable gold = tied-KV DenseAM energy + same-cell bidirectional access

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_014FAPDWQ49M5Ye3NpTndTpn

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+# M-SCALE EP TRAINER — COST ALGEBRA + SEARCH SPEC (2026-07-13)
+
+TARGET OBJECT: a TinyStories-class LM with M = 1–5M ANALOG-TRAINED weights, transformer-shaped per COMPONENT_HW_MAP.md (crossbar MVMs, divisive norms, entropic softmax, gated MLP; token embedding + LM head digital at the boundary), TRAINED end-to-end by Equilibrium Propagation two-phase local updates on the physical substrate. Inference-only hardware scores ZERO here. The $150–260 rung-A tile (CLOCKLESS_ANALOG_MVP_PLAN.md) is NOT the subject.
+NULL HYPOTHESIS (what you must beat): HW_FIRST_PRINCIPLES_SEARCH.md rung-C verdict — "the M-scale training claim lives ONLY on partner CIM silicon (UIUC), conditional on two unverified die modes; no purchasable substrate survives rung C." You win by producing a purchasable or self-owned path to grade ≥B (defined in §2.3) at M scale in a lower budget band, or any credible grade-A(M) path at any band. Doctrine: COTS / eval boards / FPGA / partner silicon — never tapeout.
+Source tags [D][F][C][M][H][A][P][X] = the audited numbers in HW_FIRST_PRINCIPLES_SEARCH.md (2026-07-13). New prices below were live-checked 2026-07-13 (DigiKey/Mouser); treat every single-quantity price as ±10% and re-verify at order time [D §6.5].
+
+## 1. COST ALGEBRA
+TotalCost = N_phys · c_cell + C_periphery + C_integration,  with  N_phys = M / R.
+- N_phys = physical trainable cells. R = time-multiplex reuse factor: one physical tile/row/block serves R logical weight tiles; weights stream between physical cells and a backing store between residencies.
+- c_cell = all-in cost per physical trainable cell (device + its share of the local update/contrast circuit + trim). Measured anchors: discrete twin edge $19–33/cell (8-edge board $150–260 [D]); digipot edge $19–31/cell all-in, $0.45/wiper raw (MCP4451-103E/ST quad, $1.80 DigiKey [H]); UIUC 28nm SRAM-CIM bank $1.1–1.9k BOM for a block-scale array [P] → c_cell ≈ $10⁻³–10⁻² only when integrated.
+- C_periphery = DAC/ADC boundary, nudge injectors (OTA class), norm/softmax cells, θ-readout chain, backing store + its bus, harness host (PYNQ-Z2 $178.44 LCSC [P]). Backing-store SILICON is cheap: 5M weights × 8b = 40 Mbit ≈ ten 4-Mbit FRAMs (CY15B104QN-50SXIT $12.74, 1,732 in stock DigiKey; MB85RS4MTYPF $17.38) ≈ $130–175, or pennies as SRAM/DDR on the host. The real periphery cost is (a) the RESTORE PATH — DACs or program-pulse drivers running at the §2.1 bandwidth — and (b) null/offset engineering: per-edge trims do not scale to 10⁵–10⁶ cells; budget auto-zero front-ends and architectural zeroing ([D]: the zero-contrast null, not the BOM, is the critical path).
+- C_integration = boards, gateware, bring-up at LOADED labor rates + one respin. Precedent: UIUC $1.1–1.9k BOM but $20–40k loaded labor [P]; FPGA harness gateware 1–3 eng-months [X].
+- Feasibility frontier (must be computed per candidate): c_cell ≤ Band / (M/R). Worked at M=2.5M: $3k band, R=6 (one transformer block resident) → N_phys=4.2·10⁵ → c_cell ≤ $0.0072 → integrated cells only; R=2,500 (N_phys=1,000, one 32×32 tile) → c_cell ≤ $3 → discrete/digipot enters, but the §2 swap wall must then be paid. Report your (R, N_phys, c_cell, BW_load) point explicitly.
+
+## 2. WHAT BOUNDS R FROM ABOVE
+Reference workload for all arithmetic: M=2.5M (d=192, L=6 blocks, ≈12d² ≈ 4.4·10⁵ weights/block), b=8 stored bits (≥7 effective, §3), batch·seq = 2048 tokens/step, N_steps = 4.9·10⁴ (100M tokens) or 4.9·10⁵ (1B tokens), nudged relaxation K=3 (map B.12). Scale to your M.
+2.1 WEIGHT-SWAP BANDWIDTH AND TIME.
+- Activation-buffered regime (each tile loaded once per pass, the whole batch streamed through it while resident): T_swap/step = 2·M·b / BW_load — note this is R-INDEPENDENT; bandwidth, not R, is the wall, R only divides cost. 2Mb = 40 Mbit/step: at 50 Mb/s (SPI/QSPI class) → 0.8 s/step → ≈11 h of pure swap per 100M-token run (fine; ×10 at 1B = 4.6 d); at I²C 400 kb/s → 100 s/step → ≈57 d (DEAD). The factor 2 = one forward-sweep load + one reverse-order nudged/feedback-sweep load per step.
+- Unbuffered / sub-block-streamed regime (weights restream per token): traffic = 2·N_tok·M·b = 4 Pbit per 100M-token run → needs ≥10 Gb/s sustained INTO ANALOG CELLS to finish in ~5 d. A digital DDR bus does this trivially; a DAC-per-column restore path at that rate is where the money goes — price it, per channel, at the required rate (no audited anchor exists; do NOT hand-wave it).
+- Buffering is not free of claims: batching a resident tile requires holding activations (and partial sums, if the tile is smaller than a matrix) at block/tile boundaries — see 2.3 last bullet.
+2.2 SWAP ENERGY AND CELL ENDURANCE. E_swap = 2·R·N_steps·N_phys·b·e_write = 2·N_steps·M·b·e_write. SRAM/register writes ~pJ/b → joules per run, free. If the PHYSICAL cell is reprogrammed each residency, each cell sees 2·R·N_steps writes/run: at R=6 → 5.9·10⁵ (100M tok) to 5.9·10⁶ (1B). Qualified endurance: flash 10⁴–10⁵ DEAD; Knowm memristor qualified 10⁴ DEAD [M]; RRAM ~10⁶ MARGINAL at 100M / DEAD at 1B, ~10⁸ OK; PCM ~10⁷–10⁹ OK-ish; SRAM / capacitor / digipot-volatile-register unlimited. Verify endurance AND write time per part — [C] precedent: 0.7–4·10⁷ pulses/cell = months–years of write time killed all COTS CIM. Program-pulse energy (nJ–µJ) × 2·N_steps·M·b can also dominate the power budget — show it.
+2.3 BACKING-STORE TECHNOLOGY → CLAIM GRADE AT M SCALE. "R6 sentence" = the public claim the build licenses. If a weight lives digitally between uses, the rung-A clockless sentence is dead by construction; what survives is graded:
+- GRADE A(M): no digital representation of any weight or gradient exists at any time during training. Backing store analog (held charge, analog floating gate) with analog transport, or R small enough to be weight-stationary. Digital allowed only at the token/label boundary (map A.1/A.10) and for phase sequencing (the M-scale concession vs rung-A). Reality check owed by any A(M) claimant: LF398-class S/H is $1.91/cell (LF398MX/NOPB, DigiKey — DEAD ×M as discrete) and droops 5 mV/min at 1 µF best-case ≈ ½ LSB @ 8b/5V FS in ~2 min → an M-cell analog store is a refresh machine; show the refresh loop closes without digitizing.
+- GRADE B+(M): the GRADIENT exists only as a physical two-phase contrast, read locally at the tile (analog outer-product / contrast cell); weights are digitized between residencies at a width ≤ the cell's effective bits — no higher-precision digital shadow. Sentence: "an M-weight transformer LM trained by physical EP dynamics, with declared digital weight logistics."
+- GRADE B−(M): as B+ plus a wider digital accumulator (16–32b shadow, ≥7b restore) — the standing map-B.16 doctrine, and the known fix for 1-LSB-quantized updates stalling near convergence (step-0 channel [H][X]). Sentence: "physical EP gradient estimator; digital weight state." Referee risk: "digital training with an analog gradient estimator" — pre-register the wording before building.
+- GRADE C(M): the nudged/feedback phase is computed digitally from digitized activations, or the analog part does forward MACs only ("analog matmul + digital loop" — the forbidden claim [C]). AUTO-REJECT: inference hardware in disguise.
+- Two EP-critical hardware modes gate every candidate (the generalized UIUC die-mode questions [P]): (i) transpose/bidirectional MVM path for Jᵀ feedback; (ii) local per-tile analog outer-product or two-phase contrast readout. Missing either, with no analog workaround → grade C, reject. Dual-copy W/Wᵀ workarounds inherit the measured 0.3–1.5% drifting mismatch channel [F][C][P][A] — fault-inject before trusting.
+- Mid-network state handling is itself a claim item: cascade single-sided θ-read (free-phase ∂E/∂θ ≡ 0, map B.13) still needs free-phase activations present at nudged time; held-analog (report the droop ledger) vs digitized (ADC inside the loop → B at best). Same fork for partial sums in sub-block tiling.
+2.4 SETTLE TIME PER PHASE. T_settle_total ≈ N_tok · L · (1+K) · t_settle (≈4 settle events/token/block; K=3). At 100M tok, L=6: t_settle 10 µs → 6.7 h; 100 µs → 2.8 d; 1 ms → 28 d MARGINAL. At 1B tok: 10 µs → 2.8 d; 100 µs → 28 d MARGINAL; 1 ms → 280 d DEAD. Classes: discrete RC boards 10 µs–1 ms [D-class]; digipot settle math was off ~10× in the proposal — recompute, don't quote [H]; CIM ns–µs [C][P].
+2.5 WALL-CLOCK GATE. T_train ≈ T_settle_total + N_steps·(2Mb/BW_load) + T_update_writes + harness overhead (measure it; USB/host round-trips killed proposals before [X]). One full TinyStories run (state your token count in 100M–1B): ≤14 d PASS; 14–60 d MARGINAL; >60 d DEAD (the [C] kill rule).
+
+## 3. TOLERANCE FLOOR (measured, cascade E-tier, 42.7M-weight reference — binding at 1–5M until re-measured; from COMPONENT_HW_MAP.md)
+- Weight precision: ≥7-bit EFFECTIVE after mismatch/INL/drift. Measured: wq8 FREE (ΔCE +0.004, cos_clean 0.96); wq6 MARGINAL (+0.051, 0.81); wq4 DEAD (+2.23). Precedent trap: digipots are 8b by construction but wiper INL → 5–6 effective bits raw; per-edge cal required [H]. "Effective bits under drift/limit-cycle" must be measured, not datasheet-copied (the unanswered CLLN question [P]).
+- Forward path: additive state noise ≤1% (σ=1e-2) FREE; device mismatch ~3% FREE (10% MARGINAL: +0.042, 0.78 on norms); multiplier/gate gain error ≤10% FREE; RoPE phase error 0.03 rad (~2°) FREE.
+- Error channel (feedback/nudged path): ≤10% noise FREE. The β-floor/ramp schedule is the SNR lever; nudge amplitude is free against MULTIPLICATIVE noise (r-indifference) — ADDITIVE readout noise is what kills. ADC bits at the θ-read buy the same margin as β.
+- Every candidate maps its own measured/datasheet numbers onto these four floors line by line. Step-0 fault channels remain purchase gates: replica asymmetry 2/5/10%, Wᵀ mismatch 0.3/1.5%, 1-LSB updates @7/8/10b [D][F][H][P][X]; ADD for M scale: activation-hold droop/quantization channel (2.3 last bullet).
+
+## 4. BUDGET BANDS (all-in: parts + boards + backing store + restore path + null engineering + loaded integration labor)
+- SELF-FUNDED ≤ $3k | ADVISOR/PARTNER-SHAPED ≤ $30k | GRANT-SHAPED ≤ $150k.
+- THE PRIZE: push an M-scale TRAINING machine into the lowest possible band. Prior art to beat: the only surviving M-scale line was $20–40k loaded, grade-B-CONDITIONAL, partner-gated, 1–3 months [P]. Beating ANY coordinate counts: lower band, higher claim grade, purchasable-today instead of partner-gated, or faster wall-clock — but report all coordinates honestly.
+
+## 5. SCORING RUBRIC — report ALL six per candidate; kill rules at bottom
+1. AUDITED $ PER BAND: itemized BOM with live distributor price + stock + date per line; restore-path and null-engineering lines REQUIRED; labor at loaded rates → assign band. An uncosted critical path = FAIL (the [D] null-engineering lesson: +$25–80/board at 8 edges, unknown and probably architectural at 10⁵ cells).
+2. CLAIM GRADE AT M SCALE: A / B+ / B− / C per §2.3, with the exact R6-style sentence the build licenses, and mode-(i)/(ii) evidence from a datasheet, die document, or vendor simulator — not marketing copy.
+3. R ACHIEVED: the tuple (R, N_phys, c_cell, BW_load, regime = buffered|streamed), placed on the §1 frontier, plus a one-line statement of WHICH §2 bound binds R for this candidate (bandwidth / endurance / buffer-claim / cost).
+4. WALL-CLOCK TO TRAIN TINYSTORIES ONCE: full §2.4–2.5 arithmetic at 100M AND 1B tokens with t_settle measured-or-datasheet and the swap term shown → PASS / MARGINAL / DEAD.
+5. TIME-TO-FIRST-RESULT: weeks to (a) first measured two-phase θ-read on the real substrate, (b) first full M-scale training run. NDA, waitlist, restock, and tool-archaeology time COUNT ([C]: 6–18 mo NDA; [F]: 1–2 mo tool archaeology; [M]: unbounded restock).
+6. SUPPLY-CHAIN FRAGILITY: single-source? stock TODAY (dated screenshot or quote)? manufacturer lifecycle page, not distributor rumor (the LM13700 three-contradictory-readings fiasco [D][P][X]); precedents: Knowm all SKUs sold out [M], Okika 29 boards on Earth [F]. Name a second source or score RED.
+KILL RULES: grade C at M scale → DEAD. Wall-clock >60 d/run → DEAD. Cell endurance < 2·R·N_steps writes (when cells are rewritten) → DEAD. Any §3 floor missed without a costed mitigation → DEAD. Any capacity claim >10× the largest independently demonstrated array on that substrate requires compile/measurement evidence, not a ratio ([F]'s fabricated 600k× lesson).
+RETURN FORMAT: one table row per candidate carrying scores 1–6, then ≤10 lines of dissent: what single new fact would resurrect this candidate if killed (the [M]/[F] re-look discipline).
+
+Sources: repo audits = HW_FIRST_PRINCIPLES_SEARCH.md + COMPONENT_HW_MAP.md + CLOCKLESS_ANALOG_MVP_PLAN.md (all 2026-07-13/-11). Live prices 2026-07-13: LF398MX/NOPB $1.91 + 5 mV/min droop (digikey.com/en/products/detail/texas-instruments/LF398-MDC/7312649, analog.com lt0198 datasheet); FRAM CY15B104QN-50SXIT $12.74 / 1,732 stock, MB85RS4MTYPF $17.38 (digikey.com/en/products/detail/kaga-fei-america-inc/MB85RS4MTPF-G-JNERE2/9748469, /ramxeed/MB85RS4MTYPF-G-BCERE1/13539951); MCP4451 $1.80, PYNQ-Z2 $178.44, ALD1106/AD633/LM13700 prices = [H][P][D] audits.