RESULT 28: Stage-0 gate #1 verdict (naked resident cells need >=10-12b; T64 word-streaming exempt; qcomp = the decisive arm)

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_014FAPDWQ49M5Ye3NpTndTpn

1 files changed, 3 insertions, 3 deletions

diff --git a/docs/hardware/PROCUREMENT_T64.md b/docs/hardware/PROCUREMENT_T64.md
index 1102a84..aee014c 100644
--- a/docs/hardware/PROCUREMENT_T64.md
+++ b/docs/hardware/PROCUREMENT_T64.md
@@ -18,9 +18,9 @@ screen down.
 Per-part functional screen, in order of kill power:
 1. Basic DAC function: full-scale + zero code on both channels; reject hard failures.
 2. System settle with 64-load column: **commit ≤3 µs; kill >7 µs** (pre-registered T64 gate).
-3. ENOB after per-cell digital pre-scale calibration, 1-hr drift window: **≥7.0** — RELAX this
-   bar per the Stage-0 qup verdict (if 6-bit updates are lossless, acceptance drops to ~6 ENOB
-   and pass-rate rises).
+3. ENOB after per-cell digital pre-scale calibration, 1-hr drift window: **≥7.0** — RELAX this bar per the Stage-0 qcomp verdict (gate #1b, compute-quantization = the T64 scenario).
+   Gate #1 (naked resident updates) measured: 10b +0.012 / 8b +0.042 / 6b +0.092 vs ctl — irrelevant
+   to T64 (fp32 master lives in DDR) but rules out shadow-less resident-cell machines below 10 bits.
 4. Channel gain mismatch / INL spot-check at 4 codes (0x40/0x80/0xC0/0xFF): within the
    forward/transpose asymmetry budget from Stage-0 gate #2 (pending).
 Log pass-rate per seller lot; ≥70% pass at the relaxed bar makes the ¥3 line the plan of record.