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Diffstat (limited to 'docs/hardware/COMPONENT_HW_MAP.md')
| -rw-r--r-- | docs/hardware/COMPONENT_HW_MAP.md | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/docs/hardware/COMPONENT_HW_MAP.md b/docs/hardware/COMPONENT_HW_MAP.md index ff47123..0cae1ea 100644 --- a/docs/hardware/COMPONENT_HW_MAP.md +++ b/docs/hardware/COMPONENT_HW_MAP.md @@ -48,7 +48,12 @@ Companion docs: `HW_RESEARCH_FINDINGS.md` (softmax dossier, OLMo2 analog audit, ## D. Demo scoping (reuse-doctrine currency) -- **Demo-0 (spec target of E-tier):** single cascade block, SRAM-CIM eval module + FPGA harness + +- **⚡ 2026-07-12: Demo-0 SUPERSEDED as the first rung by CLOCKLESS_ANALOG_MVP_PLAN.md** + (user-authored): a $170–300 clockless twin-network tile (Dillavou-lineage; EP current-nudge vs CL + voltage-clamp; exact vs sign local update; no processor/converter/clock in the learning loop) + validates the physical learning primitive first. The CIM block below becomes the PARTNER rung + (rung 5 of the ladder in COLLABORATOR_BRIEF.md). +- **Demo-0 (now rung 5, partner phase):** single cascade block, SRAM-CIM eval module + FPGA harness + COTS mixer/DAC/ADC periphery; goal = demonstrate the two-phase θ-read on one block with measured tolerances. Board-BOM class: $5–20k. - **Demo-1:** time-multiplex ONE physical trainable block through L logical positions (cascade's |