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+# EP-TRAINING SUBSTRATE DOWN-SELECT — FINAL REPORT (2026-07-13)
+
+All dollar figures below are the **audit-corrected** numbers, not the proposals'. Source tags: [D]=discrete audit, [F]=FPAA audit, [C]=CIM audit, [M]=memristor audit, [H]=digipot-hybrid audit, [A]=audio audit, [P]=partner audit, [X]=mixed-signal-harness audit.
+
+## 1. Executive summary
+
+- **The cheapest satisficing path is the incumbent, price-refreshed:** a discrete ALD1106 + film-cap twin tile, sign-EP + one exact AD633JRZ reference channel, at **$150–260 audited parts** [D] — the only substrate any audit certified as genuinely grade-A-capable (rung-A R6 sentence licensable verbatim). Every challenger either forfeits grade A structurally (FPAA, digipot, CIM, harness-automated) or costs 2–8× for worse physics (memristor, Eurorack).
+- **No purchasable substrate survived rung C.** All eight audits returned rung-C DEAD or demo-scale-only; the TinyStories-class R6-C sentence lives exclusively on partner CIM silicon (UIUC), and even that is **conditional on two unverified die modes** — transpose-direction MAC and analog outer-product ADC read — without which the whole line is grade C and auto-rejected [P].
+- **Three fault-injection channels are missing from the R2 ledger and are demanded by 4+ independent audits: (i) twin-replica conductance asymmetry (2–10% systematic false contrast at β=0) [D][X], (ii) W≠Wᵀ transpose-copy mismatch (0.3–1.5%, drifting) [F][C][P][A], (iii) 1-LSB-quantized weight updates near convergence** [H][X]. All three are $0 GPU runs and must precede any purchase.
+- **The universal engineering critical path is the zero-contrast null, not the BOM:** near convergence the contrast signal (0.1–1 mV) sits 5–500× below AD633/comparator offset floors (±5–50 mV) [D][X]; wins are per-edge trims, auto-zero front-ends, and guarded pA-class retention routing — unpriced in every proposal, ~$25–80/board + real bench labor [D].
+- **Two cheap complements dominate parts of the incumbent:** a digipot tile (**$80–120** 1-edge, **$150–250** 8-edge [H]) beats film caps on retention (zero powered drift) and resolution (8-bit by construction) at grade B; Anabrid THAT (**€449 edu** [A]) is a calibrated 1-edge exact-contrast metrology bench. Neither replaces the grade-A tile; both de-risk it.
+
+## 2. Ranked comparison (audited numbers)
+
+| # | Family | Rung-A cost (audited) | Rung-B cost (audited) | Rung-C path | R1 grade | Tolerance fit | Time-to-first-result | Claim strength (R6) |
+|---|---|---|---|---|---|---|---|---|
+| 1 | **Discrete analog (incumbent class)** | 1-edge $70–120; 8-edge sign+exact **$150–260**; all-exact $230–330; 32-edge $350–700 [D] | DEAD ($12–20k + $3–15k trim labor, not the spec's rung-B object) [D] | None (punts to partner CIM) | **A (real)** — sign-EP labeled; squarer "exact" channel refuted | R2.1/R2.4/R2.7 pass; R2.8 marginal (CD4066 leak: 1 LSB in ~3–6 min typ, <1 s worst-case) [D] | 4–8 wks (null gate + 1 near-certain respin) | **Strongest**: full rung-A grade-A sentence |
+| 2 | **Partner/academic assets** | Penn: $150–400 daughterboard + $0.5–2.5k travel + **6–10 eng-wks**; exact at 32-edge +$700–1,000 [P] | UIUC: $1.1–1.9k BOM but **$20–40k loaded labor**, grade B *conditional* on die modes [P] | Only surviving rung-C path, gated on rung B proving grade B | A at Penn (hand-switched, small-n); B-conditional/C-likely at UIUC | CLLN effective bits **unmeasured** vs the 7-bit wall (their own limit-cycle paper) [P] | 2–6 wks at Penn; 1–3 mo UIUC | Rung-A sentence sign-headlined; rung-B sentence hangs on die modes |
+| 3 | **Mixed-signal harness + analog core** | Grade A $350–600 (bench on hand) / $800–1,250 self-contained; grade B $150–250 [X] | $1,800–3,500 parts + **1–3 eng-months FPGA gateware** [X] | DEAD (demo-scale ~1M only; AD3/USB path incoherent) | A only with manual boundaries; automated runs contestable | R2.8 fails overnight scripts (1 LSB per 16–160 s on 1 µF); offset war unarmed [X] | 6–10 wks | Rung-A sentence survivable in manual config; rung-B "transformer-shaped" is garnish |
+| 4 | **Digipot hybrid crossbar** | 1-edge $80–120; 8-edge $150–250; 32-edge $300–500 [H] | $3.5–7k (1024-w twin) / $8–15k (4k-w), 3–6 months [H] | DEAD (settle math off ~10×; token budget 7× short) | **B permanently** (register+bus = converter in loop) | R2.1 needs per-edge cal (wiper INL → 5–6 effective bits raw); R2.8 **beats spec** [H] | 4–6 wks rung A | Rung-B sentence only if backward transport is physical — J^T claim refuted for the workhorse topology |
+| 5 | **FPAA (Okika)** | 8-edge $300–460 sign / $450–650 exact-twin; 32-edge $900–1,000 [F] | OTC2902K program **$5.3–8k** (extra boards: no bare chips, 29 units on Earth) [F] | DEAD (~$125–250k, ms-class streaming) | B ceiling both lines (grade A structurally excluded) | FG trim beats R2.4; temperature channel unbudgeted; endurance × throughput marginal² [F] | 1–2 mo (tool archaeology) | Rung-B sentence rests on a **fabricated capacity number** (600k× ratio ≠ 600k devices; record = 3×3 VMM) |
+| 6 | **Repurposed audio/surplus** | THAT 1-edge **€449 edu** (survives); honest hidden-weight Eurorack $2.4–2.8k + 2–4 person-wks [A] | DEAD ($65–140k) | DEAD ($30M) | A technically, hollow as drawn (VCAs are one-way → hidden weights see zero contrast) | 50 µV offset budget missed 20–100×; leakage 20× over budget at 100 MΩ [A] | 2–4 wks (THAT only) | Readout-learning demo, not the sentence |
+| 7 | **Hobbyist memristor (Knowm)** | 8-edge $700–1,300; 32-edge $2.4–3.7k — **all SKUs sold out** [M] | DEAD ($31–34k for 10³ signed, over cap; sneak paths) | DEAD (endurance 200–700× over on the qualified 10⁴-cycle number) | A only with a **human phase-clock**; retention refuted (τ≈51 s ≈ film cap) | R2.8 FAIL by 3–4 orders; R2.1 ~4-bit open-loop [M] | Unbounded (restock) | Sign-EP with measured-bias caveat at best |
+| 8 | **Commercial CIM eval** | DEAD (Knowm sold out; threshold physics caps at B) [C] | DEAD as claim ($8–30k + $50–150k NRE; grade C under R1.3) [C] | DEAD (0.7–4×10⁷ pulses/cell; months–years of write time) | **C** everywhere purchasable | R2.7 category error (no τ_state exists) [C] | 6–18 mo NDA/waitlist | None licensed; "analog matmul + digital loop" = the forbidden claim |
+
+## 3. Recommended ladder — exact purchases and asks
+
+**Step 0 (this week, $0): three GPU fault-injection runs** on the 42.7M cascade reference — twin-replica conductance asymmetry at 2/5/10%, Wᵀ-copy mismatch at 0.3/1.5%, weight updates quantized to 1 LSB @ 7/8/10-bit with deadband. These gate every purchase below and are demanded by [D][F][H][P][X].
+
+**Step 1 (rung A, grade A — the flagship): refreshed incumbent tile, $150–260** [D].
+- ALD1106PBL matched quad NMOS ×5 — **$8.86–9.29 ea** DigiKey (audits disagree on cents; both live) [D]
+- AD633JRZ (SOIC, in production) ×1 exact reference — **$10.97** DigiKey, 2,186 stock [D audit price, not the proposal's $15.97]
+- LM13700M/NOPB nudge OTA ×2 — **$1.52** DigiKey (PDIP N is obsolete; **SOIC M is ACTIVE at TI** — do not lifetime-buy) [D][P][X consensus]; qualify Coolaudio V13700M clone **$1.30** synthCube as second source [X]
+- HGSEMI LM339N **$0.12** LCSC; DMMT5551-7-F **$0.072** LCSC; JLCPCB 2-layer **$2/5 boards** (+$1.5–25 ship) [D] — the jellybean savings are real but small (~$20–60/board)
+- **Add the unpriced critical-path items** [D]: auto-zero op-amp preamp on (a−b), per-edge Z-pin trims, relay/guarded routing + ≥4.7 µF weight caps (+$25–80/board); skip breadboard, go straight to PCB; budget one respin (+$20–50, 2–3 wks). Drop the "same-substrate squarer exact channel" — physically not exact (linear feedthrough + moderate-inversion exponent) [D].
+- **Enforce the 1-edge zero-contrast-null gate before any multi-edge build** (R5.3; both [D] and [P] flag this).
+
+**Step 2 (metrology complements, optional, ≤$700):**
+- Digipot 1-edge tile **$80–120** [H] (MCP4451-103E/ST **$1.80** DigiKey confirmed) — retention/resolution reference and the quantized-update testbed; grade B, honestly labeled.
+- Anabrid THAT, **€449 edu** [A] — calibrated exact-contrast 1-edge protocol (2 multipliers on board, not 4; one THAT covers one edge). Do **not** buy from behringersound.com — confirmed scam storefront [A].
+
+**Step 3 (rung A at width, $150–400 + travel): Penn ask** — see §5. Enters at 16–32 edges on reviewer-trusted apparatus; our daughterboard is the concrete gift.
+
+**Step 4 (rung B): UIUC-conditional, digipot fallback.**
+- Gate: week-1 answer on the two die modes via the group's DAC-2025 simulator/datasheet **before any hardware commitment** [P]. If both modes exist → partner CIM at $1.1–1.9k incremental BOM (PYNQ-Z2 **$178.44** LCSC [P]), grade B, doctrine path.
+- If either mode is missing: in-house digipot block, **$3.5–7k / 3–6 months** [H], accepting the twin-replica (not S/H) fork and engineered backward transport with a measured mismatch ledger entry.
+- FPAA OTC2902K (**$2,499** confirmed, 29 units world stock [F]): only if Okika edu pricing lands ≤$1.5k AND step-0 Wᵀ run passes AND someone independently compiles >10² weights on the commercial die. Otherwise skip — the capacity story is unproven at ~100× the published record.
+
+**Step 5 (rung C):** partner CIM only, unlocked by step 4. No COTS purchase exists to make here; do not budget one.
+
+## 4. Verdict vs incumbent plan: **CONFIRMED, MODIFIED**
+
+The incumbent ($170–300 discrete twin tile + partner CIM for the block rung) survived every hostile pass; no family beat it at grade A, and the challengers' rung-B "independence" stories all degraded to conditional or dead. Modifications:
+1. **BOM refresh, not redesign:** AD633JRZ $10.97 (SOIC migration for production status, not the fabricated EOL panic — AD633ANZ is in production with six-figure stock [D]); LCSC jellybeans; JLCPCB panelization. Net tile price **$150–260**, roughly the original envelope.
+2. **Move the budget from parts to the null:** add the offset/retention engineering line (+$25–80/board, auto-zero front-ends, guarded routing, electrometer-class or buffered probing — a 10 MΩ DMM on a 1 µF node is a 10 s discharge [D]).
+3. **Pre-purchase gate:** the three $0 fault-injection channels (§3 step 0) become ledger entries before any board is ordered.
+4. **Add the two cheap complements** (digipot tile, THAT) as grade-B metrology, clearly labeled.
+5. **Harden the CIM rung's contract:** the UIUC die-mode question is now the single highest-information bit in the program; ask it before the six-week clock starts.
+
+## 5. What to ask (given these findings)
+
+**Sam Dillavou (~2 weeks):**
+1. Effective weight resolution of the CLLN under limit-cycle drift, in bits — has anyone measured it against a 7-bit-equivalent wall? (Their 2505.22887 documents the drift; nobody has quantified it in our units [P].)
+2. Would the group host a **current-nudge EP vs voltage-clamp CL** head-to-head on their 32-edge apparatus if we ship an LM13700-based OTA daughterboard (+ one AD633 exact channel)? Co-authorship terms fixed before data exists [P].
+3. Their zero-contrast null protocol: how do they trim/bound the systematic false update from transistor V_T mismatch, and what per-edge trim labor does it cost at 32 edges? (Our replica-asymmetry channel, [D][X].)
+4. Example sequencing: is their DAQ switching defensible as "data, not control" under a no-periodic-signal-in-loop reading, and how would they defend it? [P audit's grade-A attack.]
+5. Ask for their measured bias-vs-β curve, if any — β is our SNR lever and the chip's operating manual (R2 note ii).
+
+**UIUC (Shanbhag group):**
+1. **The gating question:** can the ESSERC-2025 28nm banks MAC in the transpose direction, and can a per-column analog outer product be read at the ADC — yes/no per mode, from the DAC-2025 simulator or the die docs, before any board time? If either is no, the honest product is grade C and we won't claim training on it [P].
+2. If transpose-MAC is absent: cost of the dual W/Wᵀ-copy workaround on their banks (capacity, write traffic, inter-copy mismatch spec) — we'll fault-inject the mismatch number they quote.
+3. FPGA harness reuse: what exists today, and what's the realistic bring-up for a two-phase θ-read loop (their student-months, not ours)?
+4. SRAM write **energy and bandwidth** budget for rung-C weight streaming (not endurance — SRAM endurance is unlimited; [P] audit corrected this confusion).
+
+## 6. Dissents worth preserving
+
+1. **LM13700 lifecycle — three audits, three readings.** [D]: "N obsolete, M active $1.52" (correct). [P proposal]: "EOL, lifetime-buy" — audit called it half-manufactured drama. [X proposal]: inverted it ("M obsolete, N scheduled"). Consensus for the record: **SOIC LM13700M is ACTIVE at TI**; the clone V13700M ($1.30) is a qualified fallback, not a necessity. Small price disagreements persist ($1.52 vs $1.70) — both audited-live.
+2. **The grade-A frontier for automated harnesses is genuinely unsettled.** [X] proposed an acyclicity rule (DAC-held static boundaries ≠ processor in loop, Dillavou-lineage precedent); its own audit called that a redefinition, and [P]'s audit called Penn's DAQ sequencing a periodic control signal. The spec (R5.4) is ambiguous between "human static switches only" and "no state-dependent feedback." This needs a pre-registered ruling before any grade-A publication, or referees will make it for us.
+3. **Knowm was killed partly for a fixable reason.** The sold-out shelf and the 51-s retention refutation are the kills, but the **anti-symmetric H-bridge in-situ write is the only genuinely local, genuinely analog NVM update rule any proposal produced** [M audit conceded "credit where due"]. If Knowm restocks and a batch shows longer retention (dopant-dependent; only one published measurement exists), the 1-edge tile at ~$370 deserves a re-look as a *second* grade-A physics demonstration.
+4. **FPAA rung B was killed on a fabricated number, not on physics.** The continuous-time subthreshold settle on the OTC2902 is the only COTS grade-A-*physics* forward path outside the discrete family [F audit: "the one honest grade-A physics item"]. The kill is capacity (record = 3×3 VMM) and supply (29 boards). A cheap falsification exists: pay edu pricing for one board, try to compile a 10²-weight block. If it works, the self-owned rung B resurrects at ~$5–8k.
+5. **Price hygiene cuts both ways.** The discrete audit itself mispriced AD633ANZ ($20.85 vs $21.48 across two audits) and ALD1106PBL appears at $8.28/$8.86/$9.29 in three documents — all "live-checked." Treat every single-quantity figure above as ±10% and re-verify at order time; nothing in the ranking turns on it.
+6. **The audio family's one survivor is under-used.** [A] killed the Eurorack flagship (rightly — one-way VCAs break reciprocity) but certified the THAT €449 tile "on its own merits." No other family offers calibrated multipliers + true integrators + 10-turn pots for 1-edge exact-contrast metrology at that price; it dissents against the assumption that the metrology tile and the learning tile must be the same object.
+
+---
+*Generated by an 18-agent adversarial workflow (8 substrate explorations x hostile audits x synthesis), 2026-07-13. Raw transcripts: workflows/wf_262b1851-5e7.*