diff options
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/campaign/CASCADE_ABLATION_PLAN.md | 19 | ||||
| -rw-r--r-- | docs/hardware/PROCUREMENT_T64.md | 6 |
2 files changed, 22 insertions, 3 deletions
diff --git a/docs/campaign/CASCADE_ABLATION_PLAN.md b/docs/campaign/CASCADE_ABLATION_PLAN.md index d8e5bb3..7542863 100644 --- a/docs/campaign/CASCADE_ABLATION_PLAN.md +++ b/docs/campaign/CASCADE_ABLATION_PLAN.md @@ -568,6 +568,25 @@ direction), not training-under-fault; wave-2 = co-training with faults injected +### RESULT 28 (2026-07-16): STAGE-0 HW GATE #1 — naked analog-resident updates need >10 bits; T64's word-streaming scenario measured next. +Protocol: arms7 (resume s45000 -> 55000, ctl 1.2678). --qup_bits = weights snapped to an ABSOLUTE +per-tensor grid after every update, stochastic rounding (= analog-resident cells, NO shadow). +| levels | best CE | tax vs ctl | +|---|---|---| +| fp32 (ctl) | 1.2678 | — | +| 10-bit | 1.2795 | +0.012 | +| 8-bit | 1.3096 | +0.042 | +| 6-bit | 1.3598 | +0.092 | +Monotone dose-response; clean (zero guards). Readings: +- NAKED resident-cell training (updates quantized at write, no digital shadow) needs >=10-12 bits + — this is the measured version of why in-memory analog UPDATE machines die on write resolution. +- T64 is NOT this scenario: word-streaming keeps the fp32 master in Zynq DDR; the 8-bit DAC is a + COMPUTE element. The correct T64 gate = --qcomp_bits (compute on grid-snapped weights, + fp32 master gets updates; mathematically identical to resident-cells + 24b shadow accumulator). + qcomp8/6/4 arms running (gate #1b). +- Procurement impact: the Y3/pc AD7528 line is unaffected either way (its role is compute); + the acceptance ENOB bar keys on the qcomp verdict. + ### RESULT 27 (2026-07-15): K-SATURATION ACROSS TRAINING (Alexi's challenge answered with data). Challenge (Alexi Gladstone): K=3 nudge sweeps seems very few; as training roughens the landscape, more sweeps may be needed absent a convexity argument. diff --git a/docs/hardware/PROCUREMENT_T64.md b/docs/hardware/PROCUREMENT_T64.md index 1102a84..aee014c 100644 --- a/docs/hardware/PROCUREMENT_T64.md +++ b/docs/hardware/PROCUREMENT_T64.md @@ -18,9 +18,9 @@ screen down. Per-part functional screen, in order of kill power: 1. Basic DAC function: full-scale + zero code on both channels; reject hard failures. 2. System settle with 64-load column: **commit ≤3 µs; kill >7 µs** (pre-registered T64 gate). -3. ENOB after per-cell digital pre-scale calibration, 1-hr drift window: **≥7.0** — RELAX this - bar per the Stage-0 qup verdict (if 6-bit updates are lossless, acceptance drops to ~6 ENOB - and pass-rate rises). +3. ENOB after per-cell digital pre-scale calibration, 1-hr drift window: **≥7.0** — RELAX this bar per the Stage-0 qcomp verdict (gate #1b, compute-quantization = the T64 scenario). + Gate #1 (naked resident updates) measured: 10b +0.012 / 8b +0.042 / 6b +0.092 vs ctl — irrelevant + to T64 (fp32 master lives in DDR) but rules out shadow-less resident-cell machines below 10 bits. 4. Channel gain mismatch / INL spot-check at 4 codes (0x40/0x80/0xC0/0xFF): within the forward/transpose asymmetry budget from Stage-0 gate #2 (pending). Log pass-rate per seller lot; ≥70% pass at the relaxed bar makes the ¥3 line the plan of record. |