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diff --git a/hw_sim/NOTES.md b/hw_sim/NOTES.md index ace5528..bb616f5 100644 --- a/hw_sim/NOTES.md +++ b/hw_sim/NOTES.md @@ -21,3 +21,14 @@ DESIGN OPTIONS to clear the commit gate (for Dillavou session): (c) accept 3.14 us: wall-clock 9-14 d -> ~5% slip, not a cliff. NEXT (v1.1): resistor-mismatch Monte Carlo -> ENOB-after-cal proxy; op-amp noise integration vs contrast floor; then stage C = SPICE-in-the-loop EP training (8x8 toy). + +## OPEN QUESTION FOR THE DILLAVOU SESSION (user-parked, 2026-07-17) +Bus-capacitance settle (the v1 finding): naive 64-on-one-bus = 5.4 nF -> 16.6 us (killed). +Candidate fixes to put to the experts, in our preference order: + (b) bus segmentation 2x32 + dual TIA, digital sum (~2.2 us, no new parts) — current favorite; + (a) faster TIA (OPA356-class 50 MHz, $1-2) (~1.4 us); + (user idea) time-multiplexed bucket rotation with discharge/precharge phases — maps to real + segmented-bus + precharge techniques; feasibility/complexity tradeoff = expert question; + (c) accept 3.14 us (5% schedule slip). +None of this blocks the sim line: v1.1 (mismatch MC / ENOB, noise integration) and stage C +(SPICE-in-the-loop toy training) proceed independently of which fix wins. |