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diff --git a/hw_sim/NOTES.md b/hw_sim/NOTES.md new file mode 100644 index 0000000..ace5528 --- /dev/null +++ b/hw_sim/NOTES.md @@ -0,0 +1,23 @@ +# hw_sim ledger + +## v0 (cell_v0.py, 2026-07-17): behavioral sanity +- 64-branch settle 1.14 us with ASSUMED 60 pF node — later shown ~100x optimistic. +- Two-phase offset rejection x376 (5 mV Vos). + +## v1 (cell_v1.py, 2026-07-17): datasheet-anchored — FIRST REAL DESIGN VERDICT +Anchors: AD7528 R=11k typ, R_eq(code) 0.8R-2R, C_OUT 50-120 pF/chip, settling 350/400 ns +(the chip is never the bottleneck); MCP6022 GBW 10 MHz, Vos max 500 uV. +KEY PHYSICS: 64 OUT pins share the column bus -> C_bus = 64 x ~85 pF = 5.4 nF. +E1 (settle, commit <=3 us / kill >7 us): + naive (R_f=10k, no comp) 16.6 us KILLED + R_f=10k + C_f 93 pF 8.2 us killed + R_f=3k + C_f 170 pF 5.3 us survives kill, misses commit + R_f=1k + C_f 294 pF 3.14 us 5% over commit — borderline +E2 at (1k, 294pF): Vos 500 uV -> single-read 2.71 mV, two-phase differential 0.88 uV + = x3088 rejection, 100x under the 0.1 mV contrast floor. Offset story SOLID. +DESIGN OPTIONS to clear the commit gate (for Dillavou session): + (a) faster TIA: GBW 50 MHz class (e.g. OPA356/OPA2356 ~$1-2) -> projected ~1.4 us; + (b) bus segmentation: 2x32 loads, two TIAs, digital sum -> C_bus/2 -> ~2.2 us at 10 MHz; + (c) accept 3.14 us: wall-clock 9-14 d -> ~5% slip, not a cliff. +NEXT (v1.1): resistor-mismatch Monte Carlo -> ENOB-after-cal proxy; op-amp noise integration +vs contrast floor; then stage C = SPICE-in-the-loop EP training (8x8 toy). |