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diff --git a/hw_sim/NOTES.md b/hw_sim/NOTES.md index 2bac023..eee68c6 100644 --- a/hw_sim/NOTES.md +++ b/hw_sim/NOTES.md @@ -67,3 +67,20 @@ differential resistive columns with: per-bit ladder mismatch (fixed device), per NEXT candidates (autonomy line): scale toy to 32x32 (overnight class); add settle-transient into the loop (replace DC solves at the found (R_f,C_f) point) to couple timing and training; port the ride/beta story onto the circuit noise floor (nudge amplitude sweep vs 139 uV). + +## Energy ledger (energy_ledger.py, 2026-07-17): SPICE core + datasheet periphery vs digital +SPICE-measured analog network core: 2.87 pJ/MAC (resistive burn over the 4.2 us discrete dwell). +| scenario | pJ/MAC (wiring 1-3x band) | vs digital INT8 system 0.3-1 pJ/MAC | +|---|---|---| +| MVP discrete parts | 487-1462 | loses ~1000x (op-amp quiescent x long dwell + discrete ADC) | +| T64 word-streaming | 587-1562 | loses ~1000x (+ reload/DRAM tax) | +| Integrated weight-stationary (coherent: C/100 -> 100 ns dwell) | 0.21-0.63 | **0.5x-4.8x: parity to ~5x win, ADC-dominated** | +HONEST CONCLUSIONS: +1. The boards (MVP/T64) are trainability demos, never efficiency demos — say it before referees do. +2. The integrated projection at 8-bit lands at PARITY-TO-5x, not the 10-100x of CIM marketing; + the residual is the ADC tax. Paths beyond: fewer/narrower reads, analog inter-layer + accumulation, low-precision contrast reads. +3. EP's energy contribution is CATEGORICAL, not per-MAC: it makes TRAINING possible on analog + fabric at all (inference-only CIM can't train; digital training is the displaced baseline). +4. Method: analog side SPICE-measured (+-2-3x wiring band), digital side literature constants + (Horowitz/H100 envelope) — the standard comparison protocol, uncertainty stated. |