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diff --git a/hw_sim/NOTES.md b/hw_sim/NOTES.md index eee68c6..70cf1e6 100644 --- a/hw_sim/NOTES.md +++ b/hw_sim/NOTES.md @@ -84,3 +84,14 @@ HONEST CONCLUSIONS: fabric at all (inference-only CIM can't train; digital training is the displaced baseline). 4. Method: analog side SPICE-measured (+-2-3x wiring band), digital side literature constants (Horowitz/H100 envelope) — the standard comparison protocol, uncertainty stated. + +## FAB STRATEGY (plan of record, 2026-07-18, user-aligned) +JLC PCB + SMT assembly for everything; SOCKET the screened gray-market MDACs (DIP/PLCC sockets) +— machine quality + swappability/debuggability for the risky parts. Design-for-test in layout: +test points, jumpers, isolatable single-column bring-up region (first board runs Stage-1 gates +on one column). First-article batch of 5 before volume. Hand-soldering is not an option at T64 +scale (2,250 x 20 pins); even the $300 MVP goes JLC economy so identical boards can ship to +Dillavou/Sam. Toolchain endpoint: SKiDL -> KiCad -> scripted Gerber+BOM+CPL = JLC-ready order +package from the same simulated source. SPICE pre-verification (v0/v1/v1.1/Stage-C) exists to +hold respins to 1-2 x 1-2 weeks. Bonus: machine-assembled layout parasitics are REPRODUCIBLE, +narrowing the 1-3x wiring band in the settle/energy ledgers. |