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diff --git a/hw_sim/NOTES.md b/hw_sim/NOTES.md index c028783..2802538 100644 --- a/hw_sim/NOTES.md +++ b/hw_sim/NOTES.md @@ -95,3 +95,22 @@ Sam Dillavou's lab. Toolchain endpoint: SKiDL -> KiCad -> scripted Gerber+BOM+CP package from the same simulated source. SPICE pre-verification (v0/v1/v1.1/Stage-C) exists to hold respins to 1-2 x 1-2 weeks. Bonus: machine-assembled layout parasitics are REPRODUCIBLE, narrowing the 1-3x wiring band in the settle/energy ledgers. + +## JLC costing + noise-window fix (2026-07-18) +NOISE FIX QUANTIFIED (post-settle integration window, from the measured closed-loop spectrum): + T_int 0 -> 139 uV | 1 us -> 66 uV | 2 us -> 32 uV (3.2x headroom) | 5 us -> 16 uV (6.4x) + Tradeoff: read dwell 4.2 -> 5.2 us (2 us window) = ~1.3x schedule; 5 us window = ~2x. + DESIGN CHOICE: 2 us window default (3.2x headroom under the 0.1 mV floor); big-nudge lever + stacks on top. The 139 uV MARGINAL verdict is now a designed, priced fix. +JLC BOARD ESTIMATES (economy PCBA structure: setup ~$8 + stencil + ~$0.0017/SMT joint; +THT $3.5 + $0.0173/joint; from jlcpcb.com pricing pages): + 1. MVP 8-edge tile (batch of 5): PCB 2L $5-15 + SMT $25-40 + THT $10-15 + parts $80-280 + (AD633 count dominates) => $120-350 per batch (~$60-120/board marginal) vs $170-300 for ONE + hand-built => same money, five identical boards. + 2. Stage-1 single-column rig (4x AD7528 sockets + AD7606 + LF398 x8, 4-layer): $150-220/batch-5 + — well under the $500 rig budget. + 3. T64 structural: 64 column cards (32 dual-chip sockets + TIA each) ~ $33/card assembled + => ~$2.1k + backplane/carrier $0.3-0.8k + sockets $0.4-0.6k => boards+assembly ~$3-4k; + with Y3 gray chips the whole machine lands ~$10-15k (below the audited $17-22k parts line). +NEXT CPU DELIVERABLE: SKiDL source -> KiCad -> Gerber/BOM/CPL order package for board 2 +(the Stage-1 rig — first board we would actually order). |