diff options
Diffstat (limited to 'hw_sim')
| -rw-r--r-- | hw_sim/NOTES.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw_sim/NOTES.md b/hw_sim/NOTES.md index 70cf1e6..c028783 100644 --- a/hw_sim/NOTES.md +++ b/hw_sim/NOTES.md @@ -91,7 +91,7 @@ JLC PCB + SMT assembly for everything; SOCKET the screened gray-market MDACs (DI test points, jumpers, isolatable single-column bring-up region (first board runs Stage-1 gates on one column). First-article batch of 5 before volume. Hand-soldering is not an option at T64 scale (2,250 x 20 pins); even the $300 MVP goes JLC economy so identical boards can ship to -Dillavou/Sam. Toolchain endpoint: SKiDL -> KiCad -> scripted Gerber+BOM+CPL = JLC-ready order +Sam Dillavou's lab. Toolchain endpoint: SKiDL -> KiCad -> scripted Gerber+BOM+CPL = JLC-ready order package from the same simulated source. SPICE pre-verification (v0/v1/v1.1/Stage-C) exists to hold respins to 1-2 x 1-2 weeks. Bonus: machine-assembled layout parasitics are REPRODUCIBLE, narrowing the 1-3x wiring band in the settle/energy ledgers. |