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2026-07-17hw_sim: bus-settle fix menu parked as Dillavou session question (incl user's ↵Yuren Hao
precharge-rotation idea) Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_014FAPDWQ49M5Ye3NpTndTpn
2026-07-17hw_sim v1: datasheet-anchored column — C_bus=5.4nF kills naive design ↵Yuren Hao
(16.6us); best comp point 3.14us borderline vs 3us commit gate; offset rejection x3088; three design options logged Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_014FAPDWQ49M5Ye3NpTndTpn
2026-07-17hw_sim: circuit-as-code workflow stood up (PySpice/ngspice/skidl); cell_v0 ↵Yuren Hao
— 64-branch settle 1.14us (<=3us gate PASS), two-phase offset rejection x376; sync_wandb follow mode Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_014FAPDWQ49M5Ye3NpTndTpn
generated by cgit v1.2.3 (git 2.25.1) at 2026-08-19 01:26:13 +0000