| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2026-07-17 | hw_sim v1: datasheet-anchored column — C_bus=5.4nF kills naive design ↵ | Yuren Hao | |
| (16.6us); best comp point 3.14us borderline vs 3us commit gate; offset rejection x3088; three design options logged Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_014FAPDWQ49M5Ye3NpTndTpn | |||
| 2026-07-17 | hw_sim: circuit-as-code workflow stood up (PySpice/ngspice/skidl); cell_v0 ↵ | Yuren Hao | |
| — 64-branch settle 1.14us (<=3us gate PASS), two-phase offset rejection x376; sync_wandb follow mode Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_014FAPDWQ49M5Ye3NpTndTpn | |||
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index : ept.git | |
| Unnamed repository; edit this file 'description' to name the repository. | Ubuntu |
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