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2026-07-17Energy ledger: SPICE core 2.87pJ/MAC; boards lose ~1000x (trainability ↵Yuren Hao
demos); coherent integrated projection 0.21-0.63 pJ/MAC = parity-to-5x vs digital, ADC-dominated — honest range, not CIM marketing Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_014FAPDWQ49M5Ye3NpTndTpn
2026-07-17Stage C: SPICE-in-the-loop training — SPICE == behavioral == ideal ↵Yuren Hao
(0.0213/0.0213/0.0211, all 100% acc); fidelity ladder certified; 7200 ngspice solves in 26s Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_014FAPDWQ49M5Ye3NpTndTpn
2026-07-17hw_sim v1.1: ENOB-after-cal 8.51b (clears 7.0 bar; per-bit mismatch model) + ↵Yuren Hao
noise budget 138.7uV vs 100uV floor = MARGINAL -> hardware wall-1 quantified, wants big nudges Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_014FAPDWQ49M5Ye3NpTndTpn
2026-07-17hw_sim: bus-settle fix menu parked as Dillavou session question (incl user's ↵Yuren Hao
precharge-rotation idea) Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_014FAPDWQ49M5Ye3NpTndTpn
2026-07-17hw_sim v1: datasheet-anchored column — C_bus=5.4nF kills naive design ↵Yuren Hao
(16.6us); best comp point 3.14us borderline vs 3us commit gate; offset rejection x3088; three design options logged Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_014FAPDWQ49M5Ye3NpTndTpn
2026-07-17hw_sim: circuit-as-code workflow stood up (PySpice/ngspice/skidl); cell_v0 ↵Yuren Hao
— 64-branch settle 1.14us (<=3us gate PASS), two-phase offset rejection x376; sync_wandb follow mode Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_014FAPDWQ49M5Ye3NpTndTpn
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