From a6d88a18a4bfd46ab0dd487730b72dcbc3b8b5b8 Mon Sep 17 00:00:00 2001 From: Yuren Hao Date: Wed, 15 Jul 2026 10:32:26 -0500 Subject: assets/: organize into decks|figs|hw|refs|misc; scripts + gitignore repointed Co-Authored-By: Claude Fable 5 Claude-Session: https://claude.ai/code/session_014FAPDWQ49M5Ye3NpTndTpn --- assets/hw/CLOCKLESS_ANALOG_MVP_PLAN.html | 509 +++++++++++++++++++++++++++++++ assets/hw/COLLABORATOR_BRIEF.html | 98 ++++++ assets/hw/hw_mvp_explainer.html | 220 +++++++++++++ assets/hw/hw_outreach_pack.zip | Bin 0 -> 188976 bytes 4 files changed, 827 insertions(+) create mode 100644 assets/hw/CLOCKLESS_ANALOG_MVP_PLAN.html create mode 100644 assets/hw/COLLABORATOR_BRIEF.html create mode 100644 assets/hw/hw_mvp_explainer.html create mode 100644 assets/hw/hw_outreach_pack.zip (limited to 'assets/hw') diff --git a/assets/hw/CLOCKLESS_ANALOG_MVP_PLAN.html b/assets/hw/CLOCKLESS_ANALOG_MVP_PLAN.html new file mode 100644 index 0000000..a2e1e07 --- /dev/null +++ b/assets/hw/CLOCKLESS_ANALOG_MVP_PLAN.html @@ -0,0 +1,509 @@ +

Clockless analogue MVP for physical EP research

+

Prepared: 2026-07-11
+Starting point: COMPONENT_HW_MAP.md
+Scope: academic prototype, not a product demonstrator; analogue learning core; no processor, ADC, DAC, FPGA, sample-and-hold bank, phase clock, or digital optimizer in the learning loop.

+
+

1. Executive decision

+

The current $5k–$20k Demo-0 is not an MVP. It is an architecture demonstrator that tries to validate, at once, an SRAM-CIM module, bidirectional transpose reads, RoPE mixers, QK/RMS normalization, analogue softmax, SwiGLU multipliers, analogue state handling, ADC/DAC boundaries, a phase sequencer, write programming, and digital supervisory logic. A failure would be difficult to attribute to one mechanism.

+

The lower-risk research question is narrower and more publishable:

+
+

Can a reciprocal nonlinear analogue network continuously learn by a local equilibrium contrast, with the free and nudged states physically present at the same time, without a clock or processor in the learning loop?

+
+

Build that first. The recommended core is a twin-equilibrium analogue learning tile:

+ +

Recommended first populated board: 8 sign-update edges plus one exact multiplier reference channel, approximately $170–$300 excluding instruments, tax, and shipping. This is about 17×–118× below the current $5k–$20k board class. A one-edge calibration rig is approximately $70–$130.

+
+

2. What “completely analogue and clockless” can honestly mean

+

A defensible claim is:

+
+

The state evolution, nudge, local learning rule, and weight storage are continuous-time analogue processes. No periodic control signal, processor, converter, sampled state memory, or digitally computed parameter update participates in learning.

+
+

Allowed outside the claim:

+ +

A full language-model demonstration cannot honestly be entirely analogue and clockless at the token interface: symbol lookup, presentation of a sequence, cross-entropy labels, and token sampling are discrete operations. The academic MVP should therefore validate the physical learning primitive, then add a very small reciprocal attention cell as a second experiment.

+
+

3. Core topology

+
                      analogue input x          analogue target y*
+                             │                           │
+                ┌────────────┴────────────┐              │
+                │                         │              │
+                ▼                         ▼              │
+        FREE reciprocal network    NUDGED reciprocal network
+          natural RC settling        natural RC settling
+             output y0              output yβ + nudge current
+                │                         ▲              │
+                │                         │      OTA/error transconductor
+                │                         └──────────────┘
+                │
+       for every trainable edge e:
+
+          edge voltage Δv0,e               edge voltage Δvβ,e
+                    │                              │
+                    └──── local contrast cell ─────┘
+                                  │
+                         charge/discharge current
+                                  │
+                            shared weight Cw,e
+                                  │
+                     ┌────────────┴────────────┐
+                     ▼                         ▼
+             MOSFET edge in free net   MOSFET edge in nudged net
+
+

The two replicas must be laid out symmetrically and use matched transistor pairs where practical. The shared capacitor ensures both edge copies always use the same learned weight.

+

3.1 State dynamics

+

The node voltages are the states. Resistors/MOSFET conductances and node capacitances produce the relaxation automatically. Add small capacitors only where needed to set a reproducible pole and suppress oscillation; do not build a capacitor-plus-OTA integrator for every abstract model state.

+

Design target, not a theorem:

+
τ_{weight}/τ_state ≥ 10^2,     preferably 10^3.
+
+

The state should equilibrate much faster than the weight capacitors move. This time-scale separation replaces a settle detector and phase sequencer.

+

3.2 True EP nudge and the CL control

+

Populate both modes on the same board.

+

EP mode — current/force nudge. For voltage outputs, compute the output error and inject a proportional current at the nudged output. A practical small-nudge implementation is

+
I_β = -g_β (y_0-y^*)
+
+

with an LM13700-class OTA or a discrete transconductor. The polarity is chosen to push the nudged output toward the target. This crosses voltage error with current nudge and is the mode to use for the formal EP/gradient-flow claim.

+

CL mode — voltage constraint. Buffer a weighted voltage between the free output and the target and impose it on the second replica. This is easier and reproduces the demonstrated clockless Coupled Learning architecture, but it should not be called exact EP.

+

A two-position switch should select EP-current or CL-voltage nudge. That comparison is itself a useful experiment.

+

3.3 Exact local contrast

+

For a conductance-like parameter, the local energy derivative is proportional to the squared voltage drop. Use

+
C_{w,e} dV/dt_{w,e}
+ = s_e k≤ft[(\Delta v_{β,e})^2-(\Delta v_{0,e})^2],
+
+

where s_e = ±1 accounts for whether increasing capacitor voltage increases or decreases effective conductance.

+

Do not square twice. Use

+
a^2-b^2=(a-b)(a+b),
+
+

so one four-quadrant multiplier can implement an exact reference channel. The established laboratory circuit used an AD633 with op-amp conditioning and a local capacitor.

+

3.4 Low-cost sign contrast

+

The exact multiplier dominates cost. A much cheaper local rule is

+
C_{w,e} dV/dt_{w,e}
+ = s_e I_0 sgn≤ft(|\Delta v_{β,e}|-|\Delta v_{0,e}|)
+
+

outside a deadband δ, with zero current inside the deadband. Implement it with absolute-value/rectifier stages, a comparator with hysteresis, and two matched charge/discharge current sources.

+

This rule has precedent in simulated memristor EP hardware because it removes the analogue multiplier. The continuous capacitor implementation proposed here is an engineering adaptation, not an already demonstrated result. That is a legitimate research contribution, but it must be labeled correctly.

+

3.5 Freeze and retention

+

Use a mechanical toggle or relay to disconnect update current from every weight capacitor. Avoid a clocked switch matrix. Use film capacitors initially; characterize leakage and dielectric absorption. Volatile analogue weights are acceptable for an academic demonstrator, but not for a storage product.

+
+

4. Recommended hardware ladder

+

Rung A — one-edge metrology tile

+

Purpose: validate the physics before assembling a network.

+

Populate:

+ +

Estimated cost: $70–$130.

+

Required measurements:

+
    +
  1. transfer surface I_update(Δv0, Δvβ);
    2. +
  2. exact-channel gain and offset;
    3. +
  3. sign-channel boundary, hysteresis, and deadband;
    4. +
  4. zero-contrast drift at Δv0 = Δvβ;
    5. +
  5. weight retention with learning frozen;
    6. +
  6. temperature drift;
    7. +
  7. nudge linearity versus β;
    8. +
  8. time-scale ratio between node settling and weight motion.
    9. +
+

Do not build the multi-edge board until this tile gives a stable null at zero contrast.

+

Rung B — two modular four-edge cards

+

Build a four-edge card and populate two cards for eight trainable edges. Each card contains:

+ +

Recommended population: eight sign channels plus one parallel exact AD633 channel on a selected edge. This gives a continuously measured exact-versus-sign comparison without buying eight multipliers.

+

Estimated cost: $170–$300.

+

Initial task:

+ +

Do not promise XOR at eight edges. The published nonlinear clockless network used 32 twin edges for XOR. Design the card so eight identical four-edge modules can be stacked later.

+

Rung C — 32-edge replication-class network

+

Use eight four-edge cards and the sign-update rule. This approaches the scale of the published nonlinear demonstration while avoiding 32 AD633 multipliers.

+

Estimated cost: $450–$900.

+

This is still below the low end of the original plan by approximately 5.5×–44× and is large enough for a serious robustness and nonlinear-learning study.

+

Rung D — reciprocal attention microcell

+

Only after Rungs A–C work, add a transformer-adjacent cell:

+ +

For two alternatives, softmax reduces to a logistic function of a score difference, so a differential pair can replace a general N-way entropic-resistor array. This is an attention-shaped energy cell, not an OLMo2 block.

+

Estimated total including the learning core: $300–$700.

+
+

5. Costed options

+

Budgetary single-quantity catalogue prices checked on 2026-07-11; prices exclude tax, shipping, instruments, assembly labor, and rework.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ItemPlanning roleUnit price usedPlanning quantity, 8-edge boardExtended
ALD1106PBLmatched N-MOS array; two twin edges/package$9.294$37.16
AD633ANZexact four-quadrant contrast multiplier$21.480, 1, or 8$0 / $21.48 / $171.84
TLV274IPWRquad rail-to-rail op amp$1.436–8$8.58–$11.44
LM13700dual OTA; output nudge/current sources$1.701–2$1.70–$3.40
LM339-class comparatorsign/deadband channelsabout $0.672–4about $1.34–$2.68
CD4066-class switchoptional static freeze/routingabout $0.73–$0.972–4about $1.46–$3.88
Film capacitorsweight storageabout $0.63 at 1 µF8–12about $5–$8
Diodes, resistors, trimsrectifiers, limits, biasing—lot$15–$40
PCB/protoboard, headers, test pointsphysical implementation—lot$35–$120
Power rails, protection, spare partslaboratory overhead—lot$30–$90
+

Resulting envelopes:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
VariantEstimated build costRecommendation
One-edge exact/sign calibration tile$70–$130Build first
8-edge sign-only$140–$250Cheapest useful network
8-edge sign + one exact reference channel$170–$300Recommended MVP
8-edge all-exact AD633$300–$500Only after reference channel works
32-edge sign-update network$450–$900Replication-class nonlinear demo
Reciprocal two-token attention add-on+$100–$250Phase 2 only
+

Aggressive transistor substitution

+

A CD4007UBE costs about $0.89 and contains a CMOS dual complementary pair plus inverter. It can be explored on the one-edge tile, but it is not the main-board recommendation: matching, body connections, and device operating region become the dominant uncertainty. Saving roughly $30 of matched-transistor cost on an eight-edge board is not worth sacrificing the experiment’s interpretability.

+
+

6. Delete list for the original plan

+

For the academic MVP, delete these entirely:

+ +

Keep or replace as follows:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Original functionMVP replacement
MVM/crossbarpatchable reciprocal nonlinear resistor network
state integratorsnatural RC/KCL state dynamics
sequential free/nudged phasestwo continuously operating physical replicas
DAC nudgeOTA current injection
digital phase memorysimultaneous physical state comparison
outer-product update/programminglocal capacitor charge/discharge
FPGA controlmanual boundary selection and learn/freeze
ADC telemetrybuffered scope/DMM observation outside loop
+
+

7. Experimental matrix

+

The cleanest paper is not merely “it learned.” It should isolate the choices that make the clockless implementation possible.

+

Factor 1 — nudge type

+ +

Factor 2 — local update

+ +

Factor 3 — device quality

+ +

Factor 4 — nudge magnitude

+ +

Factor 5 — operating conditions

+ +

Proposed acceptance criteria, to be declared before network training:

+
    +
  1. no periodic control signal in the learning loop;
    2. +
  2. no processor, ADC, DAC, or stored free-phase sample used for an update;
    3. +
  3. exact reference channel has a stable zero-contrast null;
    4. +
  4. sign channel agrees with the exact channel on update direction in at least 95% of the specified operating grid;
    5. +
  5. frozen weights remain within the chosen tolerance over the measurement interval;
    6. +
  6. loss decreases consistently across multiple resets, with all failures reported;
    7. +
  7. EP-current and CL-voltage modes are labeled separately.
    8. +
+
+

8. Six-week execution plan

+

Week 1 — SPICE and one-edge schematic

+ +

Week 2 — one-edge breadboard

+ +

Week 3 — one-edge characterization

+ +

Week 4 — first four-edge card

+ +

Week 5 — eight-edge network

+ +

Week 6 — robustness and paper figures

+ +
+

9. Claims this MVP can and cannot support

+

It can support

+ +

It cannot support

+ +

A passive reciprocal network avoids the adjoint/transposed-Jacobian problem by construction, but it also excludes normal non-reciprocal attention. The transformer connection must therefore use tied, energy-based attention or be deferred to an active-adjoint phase.

+
+

10. Why this is the better academic MVP

+

It tests one scientific claim at a time. Every expensive item in the original plan exists to preserve a nearly complete transformer block. That is appropriate after the physical learning primitive is established, not before it.

+

The proposed sequence produces publishable intermediate results even if the final nonlinear task fails:

+ +

The main recommendation is therefore:

+
+

Build the $70–$130 one-edge tile, then the $170–$300 eight-edge hybrid board. Do not purchase a CIM evaluation module, FPGA, DAC/ADC bank, or softmax hardware for the MVP.

+
+
+

11. Primary references used

+
    +
  1. Sam Dillavou et al., “Machine Learning Without a Processor: Emergent Learning in a Nonlinear Electronic Metamaterial,” arXiv:2311.00537v2 / PNAS (2024). Demonstrated a fully analogue, clockless nonlinear twin-resistor network; 32 twin edges; local capacitive learning; XOR and nonlinear regression. Its implemented rule is Coupled Learning.
    2. +
  2. Sam Dillavou et al., “Understanding and Embracing Imperfection in Physical Learning Networks,” arXiv:2505.22887v2 (2026 revision). Characterizes bias, limit cycles, and system-agnostic suppression of analogue learning imperfections.
    3. +
  3. Joshua A. McGinnis, Xinbo Li, and Yoichiro Mori, “Coercivity and Local Convergence of Physical Learning in Linear Circuits,” arXiv:2606.15443 (2026). Distinguishes EP’s force/current nudge from CL’s voltage constraint and analyzes their gradient-flow structure.
    4. +
  4. Seung-Hyun Oh et al., “Memristor Crossbar Circuits Implementing Equilibrium Propagation for On-Device Learning,” Micromachines 14(7):1367 (2023). Proposes simultaneous free/nudged networks and a sign-only fixed-step update to remove analogue multipliers; results are simulation-oriented for memristor programming.
    5. +
  5. I. M. Elfadel and J. L. Wyatt, “The ‘Softmax’ Nonlinearity: Derivation Using Statistical Mechanics and Useful Properties as a Multiterminal Analog Circuit Element,” NeurIPS 1993. Establishes reciprocal/passive circuit properties of an entropic softmax element.
    6. +
  6. “How to Train Your Resistive Network: Generalized Equilibrium Propagation and Analytical Learning,” arXiv:2602.03546 (2026). Gives a single-network projector-based route for linear resistive networks; useful as a future replica-reduction direction, not the first nonlinear build.
    7. +
\ No newline at end of file diff --git a/assets/hw/COLLABORATOR_BRIEF.html b/assets/hw/COLLABORATOR_BRIEF.html new file mode 100644 index 0000000..48df78c --- /dev/null +++ b/assets/hw/COLLABORATOR_BRIEF.html @@ -0,0 +1,98 @@ +

Backprop-free training of transformers — results and a staged hardware program

+

One-page brief for hardware-side collaborators · rev. 2026-07-12 · Yuren Hao (UIUC)

+

The idea in three sentences

+

We train standard multi-layer transformers with Equilibrium Propagation on a layered energy: +training consists of two relaxation phases and a local contrast update per weight — no +backpropagation anywhere — and inference is an ordinary forward pass. On GPU this now works at +language-model scale with essentially no quality gap to backprop. The hardware program starts with +the cheapest object that can validate the physical learning rule — a clockless twin-network +analog tile (~$300) — and climbs rung by rung to an in-memory-compute transformer block.

+

GPU-scale results (2026-07, measured)

+ +

Measured fault tolerances (fault injection at the trained model)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
faultfreemarginaldead
weight precision8-bit (ΔCE +0.004)6-bit (+0.05)4-bit
forward state noise1%——
error-channel (nudge) noise10% relative30%—
divider mismatch / gate gain / phase error3% / 10% / 0.03 rad10% / — / 0.1 rad—
+

Under every non-fatal fault the learning signal tracks the faulted network (gradient cosine ≈ 0.97 +invariant): the rule co-adapts to the device. The only hard spec is ~7-bit effective weights.

+

The hardware ladder (each rung publishable alone)

+
    +
  1. One-edge metrology tile ($70–130): twin MOSFET edge, shared weight capacitor, exact + (difference-of-squares) and sign-only local update channels, OTA current nudge — no processor, + converter, clock, or sampled memory in the learning loop.
    2. +
  2. 8-edge twin network ($170–300): nonlinear regression; EP current-nudge vs Coupled-Learning + voltage-clamp on one board; exact-vs-sign update comparison; measured bias-vs-nudge-magnitude + curve (the same β-SNR law we measured in simulation).
    3. +
  3. 32-edge network ($450–900): replication-class nonlinear tasks, robustness study.
    4. +
  4. Reciprocal attention microcell (+$100–250): two tokens, one head, energy-based attention.
    5. +
  5. CIM transformer block (partner phase): analog MVM + in-situ two-phase EP weight update — + the piece no shipping analog-AI chip has (all are inference-only or on-chip-backprop).
    6. +
  6. North star: a few-M-parameter TinyStories LM trained on analog hardware.
    7. +
+

What we bring / what we ask

+

Bring: the trained models and recipe, the estimator theory (β-SNR law, stability walls), the +measured tolerance ledger, SPICE-first costed build plan, and parts funding (rungs 1–3 are <$1k). +Ask (rungs 1–3): bench access, analog-design mentorship, and/or a student who enjoys discrete +analog — six-week plan, instruments = a scope and a DMM. Ask (rung 5): a CIM/mixed-signal +partnership where the substrate expertise is yours and the learning rule is ours.

+

(Detail: CLOCKLESS_ANALOG_MVP_PLAN.md — full BOM, schedule, acceptance criteria, claim limits; +COMPONENT_HW_MAP.md — per-operation analog mapping + tolerance status.)

\ No newline at end of file diff --git a/assets/hw/hw_mvp_explainer.html b/assets/hw/hw_mvp_explainer.html new file mode 100644 index 0000000..4114648 --- /dev/null +++ b/assets/hw/hw_mvp_explainer.html @@ -0,0 +1,220 @@ + + + + +无时钟模拟学习板 — 结构图解（给不懂硬件的人） + + + +
+ +

无时钟模拟学习板：它长什么样、为什么能学习

+

+一句话：这块板子上同时活着两份一模一样的电路——一份自由地"回答问题"（FREE），一份的输出被轻轻拉向正确答案（NUDGED）。 +每个"权重"是一颗电容，它不停地比较自己在两份电路里的受力差异、朝着缩小差异的方向缓慢充放电。 +没有处理器、没有时钟、没有数模转换——物理本身在做训练。 +把鼠标悬停在图里任何东西上看它是什么。 +

+ + + + + + + + + + FREE 网络（自由态） + 自然弛豫，输出 = 网络自己的回答 ŷ + + + + + + + x₁ + + x₂ + + + + h + + + + ŷ + + + + + + + + + + + + + + + NUDGED 网络（微推态） + 同样的电路 + 输出被轻拉向目标 y* + + + + + + x₁ + + x₂ + + h + + + + ŷβ + + + + + + + + + + + + + + + y* + + + + + 电流微推 (β) + + + + 共享权重 + 学习单元（每条边一套） + + + + + + + + learn / freeze + + + + + + 示波器 + + +

悬停任何元素查看解释 · 紫框 = 学习单元（对比 + 电容）· 绿 = 权重/目标相关 · 蓝 = FREE · 橙 = NUDGED

+ +

ML ↔ 电路 词典

+ + + + + + + + + + +
机器学习里的板子上的备注
激活值 z节点电压没人"计算"它——电流平衡自己找到它
权重 w一颗电容的电压（控制 MOSFET 导电性）非易失升级版 = FeFET（Zhu 组的方向）
前向传播RC 自然弛豫（~微秒）免费，且天然并行
损失的输出梯度OTA 电流 = g·(ŷ − y*)只在输出端，任何学习规则都需要这个
反向传播不存在被"双生网络 + 局部对比"替代
每个权重的梯度该边两侧压降的平方差 Δvβ² − Δv²纯局部量——只需要摸自己这条边
optimizer.step()电容充/放电（~毫秒-秒）学习率 = 充电电流大小
训练循环 / 时钟不存在两态同时物理存在 + 快慢时间尺度分离
+ +

一次"学习"是怎么发生的（其实是连续的，这里人为分步）

+
    +
  1. 摆题：手动开关把输入 x 设到两份网络上，把目标 y* 设到 OTA 上。
    2. +
  2. 瞬间稳定（微秒级）：两份网络各自弛豫。FREE 的输出是网络自己的回答；NUDGED 的输出被 OTA 拉向正确答案一点点。
    3. +
  3. 形变传播：输出端被拉动后，NUDGED 网络全身的电压分布都微微变形——离输出越远变形越小，但每条边都感受得到。这就是"credit assignment 由物理完成"。
    4. +
  4. 逐边对比（连续进行）：每条边的学习单元比较自己在两侧的压降，差异越大充电越快。方向恰好是能量下降的方向——数学上等价于梯度下降。
    5. +
  5. 慢速累积（毫秒-秒级）：权重电容比节点慢 100–1000 倍，所以在权重看来网络永远是"稳定的"——这个时间尺度差就是时钟的替代品。
    6. +
  6. 换题：手动换下一组输入/目标。重复。loss 就这样降下去（Penn 的 32 边版本已经在物理上学会了 XOR 和非线性回归）。
    7. +
+ +

造价阶梯

+

+① 单边标定件 $70–130（先证明物理） +② 8 边网络 $170–300 ← 推荐 MVP +③ 32 边 $450–900（复现 Penn 规模） +④ 注意力微单元 +$100–250 +⑤ CIM transformer block（合作方阶段） +

+ +
+诚实边界（也是给合作者的说法）：这块板子验证的是物理学习原语——无时钟双生 EP、局部模拟更新、真电流 nudge vs 电压钳制的对比—— +不是 transformer 本身。它和我们 GPU 侧共享同一条定律：nudge 幅度 vs 噪声的信噪比曲线（我们在 fp32 里测过的 β 定律，这块板会在物理里再测一遍）。 +
+ +
+
+ + + diff --git a/assets/hw/hw_outreach_pack.zip b/assets/hw/hw_outreach_pack.zip new file mode 100644 index 0000000..4737d6c Binary files /dev/null and b/assets/hw/hw_outreach_pack.zip differ -- cgit v1.2.3