From edd4b9358690c4ae6ff3513f828cc08bc86b3cf7 Mon Sep 17 00:00:00 2001 From: Yuren Hao Date: Thu, 9 Jul 2026 23:38:36 -0500 Subject: FINDINGS: 2026-07-11 consolidated hardening entry --- docs/campaign/FINDINGS.md | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) (limited to 'docs/campaign/FINDINGS.md') diff --git a/docs/campaign/FINDINGS.md b/docs/campaign/FINDINGS.md index 4b78f78..baeafca 100644 --- a/docs/campaign/FINDINGS.md +++ b/docs/campaign/FINDINGS.md @@ -760,3 +760,41 @@ certification needs a ρ>0.95 lower bound (certified a ρ=0.80 corpse). **Next: D-tier** — L12×C512 (~45M standard GPT-small) EP-vs-BP flagship + Muon arm (OmniOpt sweet spot 60–350M; Muon = digital-side, free on GPU, EP-interaction unmeasured). + +## 2026-07-11 (consolidated) — hardening day: BP-free formalized, precision gated, HW re-priced, dynamics-paper v2 shipped + +**BP-free formal audit (5.6-Sol, CPU-instrumented):** EP update verified LOCAL at every autograd site +(max block-depth 1; 108 bitwise zero-influence checks). Two fixes: bp_gate telemetry made observe-only +by default (--gate_govern opt-in) + gate_every<=0 = true off switch. test_bp_free.py (4 invariant +tests, 3s CPU) now guards the property in-repo. Claim wording: "no cross-block backprop exists in the +training loop; the only BP is a fully-disableable measurement instrument." + +**A0.4 precision gate:** TF32 == fp32 bit-for-bit on the gate (cos 0.9946) — the looped-era TF32 kill +was the edge-riding loop's disease, cascade immune. Pure-bf16 model: cos 0.9427 — production-usable, +banned from parity comparisons; HW reading: error channel survives 8-bit mantissa. + +**Speedup audit (5.6-Sol, max):** the 3.5-3.8x EP/BP gap is STRUCTURAL (work-ratio-matched); eager +headroom only 5-10% (sync-point collapse, round-0 CE reuse, param-free connected vjp graphs, d-seeded +theta vjp). compile impossible on sm_61 (Inductor needs CC>=7.0). v8 queued post-D1a. + +**Optimizer rulings:** Lion/SGD RULED OUT for EP (empirical: abl_lion2 blew @600 + prior record) — do +not resurface. OmniOpt intel: Muon = quality frontier 60-350M (its NS variants: quintic/PolarExpress/ +cubic-relaxed/Gram/low-rank — ALL matrix-matrix, ALL priced out of fully-analog; GPU-free). Analog +optimizer = factored-Adam; and under the reuse doctrine (digital-accumulate->threshold-program) +optimizer state is DIGITAL-side by design => Adam ~free on hardware, Adam-vs-Muon = algorithm question +(D1a referees). + +**HW doctrine restored + cascade re-pricing:** tapeout framing retracted (twice violated, now iron +rule in memory). Cascade cuts every hardware demand vs the looped plan: feedforward free phase = +COTS-native, depth = time-mux one trainable block (memory line-item), nudged duty -50x, leash +instrumentation deleted, SRAM-CIM (Shanbhag line) alone suffices for Demo-1 ($5-20k board BOM). + +**Dynamics paper (aep-dynamics) v2 SHIPPED (16pp):** zl-review experiment suite integrated as native +content — init/drive/saturation-margin paragraphs (§3: 200/200 emergent crossing, 0/200 crash, rho_0 +sweep 26->99%), nonlinearity axis (§4: tanh 73% Hopf vs ReLU/GELU ~50/50 at death; coexistence 0/9), +norm-penalty head-to-head + control-when spectrum + FF scope note (§5: floss 0.44 < spectral 0.65 < +jacreg 0.78 < leak 1.06 < RC 1.16; rescue 1.67 from 1e13), quantified §7 JacReg passage, full config +appendix. REVIEW_RESPONSE_zl_260710.md final (coexist 0/9 included) — both in user's hands. + +**D1a interim (L12xC512 ~45M, 4k steps, lr 1e-3):** BP 1.9169/1.9194 (s1/s2); EP arms in flight +(s1 @2800: 2.0444, cos 0.994 — slightly below C256's 1.0000, watch); Muon arms queued behind. -- cgit v1.2.3