From 7ff813044e0eb44284d060e20a148b08dd2040c1 Mon Sep 17 00:00:00 2001 From: Yuren Hao Date: Thu, 9 Jul 2026 23:21:16 -0500 Subject: =?UTF-8?q?HW:=20cascade=20re-pricing=20under=20the=20reuse=20doct?= =?UTF-8?q?rine=20=E2=80=94=20depth=20becomes=20a=20memory=20line-item=20(?= =?UTF-8?q?time-mux=20one=20trainable=20block),=20nudged=20duty=20drops=20?= =?UTF-8?q?~50x,=20leash=20instrumentation=20deleted,=20SRAM-CIM=20alone?= =?UTF-8?q?=20suffices=20for=20Demo-1=20(device=20fab=20optional)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-Authored-By: Claude Fable 5 Claude-Session: https://claude.ai/code/session_014FAPDWQ49M5Ye3NpTndTpn --- docs/hardware/HW_RESEARCH_FINDINGS.md | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'docs') diff --git a/docs/hardware/HW_RESEARCH_FINDINGS.md b/docs/hardware/HW_RESEARCH_FINDINGS.md index 0a749db..cba8f0b 100644 --- a/docs/hardware/HW_RESEARCH_FINDINGS.md +++ b/docs/hardware/HW_RESEARCH_FINDINGS.md @@ -274,3 +274,30 @@ state lives digital-side (FPGA BRAM/DDR), not in analog: **$5–20k board-level BOM + engineering time**; beyond-eval-kit in-situ arrays come from the UIUC device/circuit line (their fab, grant money). GAP-2 procurement pass (TetraMem / Anadigm FPAA / Aspinity SKU + prices) remains the open to-do it always was. + +### CASCADE RE-PRICING under the doctrine (2026-07-11, user point: "block叠加只会更便宜") + +The 2026-06-21 plan was priced for the LOOPED block — the hardest possible customer (in-situ +recurrent fabric, 150–300-step settling duty, on-chip spectral leash instrumentation). Cascade +strictly reduces every hardware demand: + +1. **Free phase = plain feedforward** ⟹ the bulk of compute is exactly what LARGE-but-FIXED COTS + (Mythic-class) sells. What the old plan could only use "cleverly" in Phase 2 is now natively fit. +2. **One physical block, L logical layers (time-multiplex).** Cascade blocks are structurally + identical — ONE trainable CIM module + weight banks emulates the whole stack sequentially. + Trainable-fabric area NO LONGER SCALES WITH DEPTH: L6→L12→L24 costs DDR/SRAM for weight sets + (negligible) + wall-clock, not more analog hardware. "叠 block" is a memory line-item. +3. **Nudged phase = 3 fb rounds, not 150–300 settling steps** ⟹ analog duty cycle drops ~50×; + retention/drift budgets relax accordingly. +4. **Leash/governor instrumentation DELETED** — free phase is unconditionally exact; the on-chip + spectral-monitoring layer the looped plan required simply does not exist here. +5. **★ SRAM-CIM suffices for Demo-1.** Time-muxing means weights are (re)loaded per layer — + endurance-free, fast-write SRAM-CIM (Shanbhag DIMA line: analog MVM + demonstrated on-chip + write-back, JSSC 2018) handles it outright. **The NVM/memristor device fab (Zhu) becomes + OPTIONAL for the demo** (kept for the non-volatile scale story) — the hardest UIUC dependency + drops out of the critical path. Demo-1 = Shanbhag-line module (or equivalent SRAM-CIM eval + fabric) + FPGA + converters, same **$5–20k board-level BOM**, now covering an L-layer + tinystories-class trainer instead of one looped block. + +Net: cascade turned depth from the cost driver into a memory line-item, and reduced the demo's +critical-path collaboration from three groups to one. -- cgit v1.2.3