Prepared: 2026-07-11
Starting point: COMPONENT_HW_MAP.md
Scope: academic prototype, not a product demonstrator; analogue learning core; no processor, ADC, DAC, FPGA, sample-and-hold bank, phase clock, or digital optimizer in the learning loop.
The current $5k–$20k Demo-0 is not an MVP. It is an architecture demonstrator that tries to validate, at once, an SRAM-CIM module, bidirectional transpose reads, RoPE mixers, QK/RMS normalization, analogue softmax, SwiGLU multipliers, analogue state handling, ADC/DAC boundaries, a phase sequencer, write programming, and digital supervisory logic. A failure would be difficult to attribute to one mechanism.
The lower-risk research question is narrower and more publishable:
Can a reciprocal nonlinear analogue network continuously learn by a local equilibrium contrast, with the free and nudged states physically present at the same time, without a clock or processor in the learning loop?
Build that first. The recommended core is a twin-equilibrium analogue learning tile:
Recommended first populated board: 8 sign-update edges plus one exact multiplier reference channel, approximately $170–$300 excluding instruments, tax, and shipping. This is about 17×–118× below the current $5k–$20k board class. A one-edge calibration rig is approximately $70–$130.
A defensible claim is:
The state evolution, nudge, local learning rule, and weight storage are continuous-time analogue processes. No periodic control signal, processor, converter, sampled state memory, or digitally computed parameter update participates in learning.
Allowed outside the claim:
A full language-model demonstration cannot honestly be entirely analogue and clockless at the token interface: symbol lookup, presentation of a sequence, cross-entropy labels, and token sampling are discrete operations. The academic MVP should therefore validate the physical learning primitive, then add a very small reciprocal attention cell as a second experiment.
analogue input x analogue target y*
│ │
┌────────────┴────────────┐ │
│ │ │
▼ ▼ │
FREE reciprocal network NUDGED reciprocal network
natural RC settling natural RC settling
output y0 output yβ + nudge current
│ ▲ │
│ │ OTA/error transconductor
│ └──────────────┘
│
for every trainable edge e:
edge voltage Δv0,e edge voltage Δvβ,e
│ │
└──── local contrast cell ─────┘
│
charge/discharge current
│
shared weight Cw,e
│
┌────────────┴────────────┐
▼ ▼
MOSFET edge in free net MOSFET edge in nudged net
The two replicas must be laid out symmetrically and use matched transistor pairs where practical. The shared capacitor ensures both edge copies always use the same learned weight.
The node voltages are the states. Resistors/MOSFET conductances and node capacitances produce the relaxation automatically. Add small capacitors only where needed to set a reproducible pole and suppress oscillation; do not build a capacitor-plus-OTA integrator for every abstract model state.
Design target, not a theorem:
τ_{weight}/τ_state ≥ 10^2, preferably 10^3.
The state should equilibrate much faster than the weight capacitors move. This time-scale separation replaces a settle detector and phase sequencer.
Populate both modes on the same board.
EP mode — current/force nudge. For voltage outputs, compute the output error and inject a proportional current at the nudged output. A practical small-nudge implementation is
I_β = -g_β (y_0-y^*)
with an LM13700-class OTA or a discrete transconductor. The polarity is chosen to push the nudged output toward the target. This crosses voltage error with current nudge and is the mode to use for the formal EP/gradient-flow claim.
CL mode — voltage constraint. Buffer a weighted voltage between the free output and the target and impose it on the second replica. This is easier and reproduces the demonstrated clockless Coupled Learning architecture, but it should not be called exact EP.
A two-position switch should select EP-current or CL-voltage nudge. That comparison is itself a useful experiment.
For a conductance-like parameter, the local energy derivative is proportional to the squared voltage drop. Use
C_{w,e} dV/dt_{w,e}
= s_e k≤ft[(\Delta v_{β,e})^2-(\Delta v_{0,e})^2],
where s_e = ±1 accounts for whether increasing capacitor voltage increases or decreases effective conductance.
Do not square twice. Use
a^2-b^2=(a-b)(a+b),
so one four-quadrant multiplier can implement an exact reference channel. The established laboratory circuit used an AD633 with op-amp conditioning and a local capacitor.
The exact multiplier dominates cost. A much cheaper local rule is
C_{w,e} dV/dt_{w,e}
= s_e I_0 sgn≤ft(|\Delta v_{β,e}|-|\Delta v_{0,e}|)
outside a deadband δ, with zero current inside the deadband. Implement it with absolute-value/rectifier stages, a comparator with hysteresis, and two matched charge/discharge current sources.
This rule has precedent in simulated memristor EP hardware because it removes the analogue multiplier. The continuous capacitor implementation proposed here is an engineering adaptation, not an already demonstrated result. That is a legitimate research contribution, but it must be labeled correctly.
Use a mechanical toggle or relay to disconnect update current from every weight capacitor. Avoid a clocked switch matrix. Use film capacitors initially; characterize leakage and dielectric absorption. Volatile analogue weights are acceptable for an academic demonstrator, but not for a storage product.
Purpose: validate the physics before assembling a network.
Populate:
Estimated cost: $70–$130.
Required measurements:
I_update(Δv0, Δvβ);Δv0 = Δvβ;β;Do not build the multi-edge board until this tile gives a stable null at zero contrast.
Build a four-edge card and populate two cards for eight trainable edges. Each card contains:
Recommended population: eight sign channels plus one parallel exact AD633 channel on a selected edge. This gives a continuously measured exact-versus-sign comparison without buying eight multipliers.
Estimated cost: $170–$300.
Initial task:
Do not promise XOR at eight edges. The published nonlinear clockless network used 32 twin edges for XOR. Design the card so eight identical four-edge modules can be stacked later.
Use eight four-edge cards and the sign-update rule. This approaches the scale of the published nonlinear demonstration while avoiding 32 AD633 multipliers.
Estimated cost: $450–$900.
This is still below the low end of the original plan by approximately 5.5×–44× and is large enough for a serious robustness and nonlinear-learning study.
Only after Rungs A–C work, add a transformer-adjacent cell:
For two alternatives, softmax reduces to a logistic function of a score difference, so a differential pair can replace a general N-way entropic-resistor array. This is an attention-shaped energy cell, not an OLMo2 block.
Estimated total including the learning core: $300–$700.
Budgetary single-quantity catalogue prices checked on 2026-07-11; prices exclude tax, shipping, instruments, assembly labor, and rework.
| Item | Planning role | Unit price used | Planning quantity, 8-edge board | Extended |
|---|---|---|---|---|
| ALD1106PBL | matched N-MOS array; two twin edges/package | $9.29 | 4 | $37.16 |
| AD633ANZ | exact four-quadrant contrast multiplier | $21.48 | 0, 1, or 8 | $0 / $21.48 / $171.84 |
| TLV274IPWR | quad rail-to-rail op amp | $1.43 | 6–8 | $8.58–$11.44 |
| LM13700 | dual OTA; output nudge/current sources | $1.70 | 1–2 | $1.70–$3.40 |
| LM339-class comparator | sign/deadband channels | about $0.67 | 2–4 | about $1.34–$2.68 |
| CD4066-class switch | optional static freeze/routing | about $0.73–$0.97 | 2–4 | about $1.46–$3.88 |
| Film capacitors | weight storage | about $0.63 at 1 µF | 8–12 | about $5–$8 |
| Diodes, resistors, trims | rectifiers, limits, biasing | — | lot | $15–$40 |
| PCB/protoboard, headers, test points | physical implementation | — | lot | $35–$120 |
| Power rails, protection, spare parts | laboratory overhead | — | lot | $30–$90 |
Resulting envelopes:
| Variant | Estimated build cost | Recommendation |
|---|---|---|
| One-edge exact/sign calibration tile | $70–$130 | Build first |
| 8-edge sign-only | $140–$250 | Cheapest useful network |
| 8-edge sign + one exact reference channel | $170–$300 | Recommended MVP |
| 8-edge all-exact AD633 | $300–$500 | Only after reference channel works |
| 32-edge sign-update network | $450–$900 | Replication-class nonlinear demo |
| Reciprocal two-token attention add-on | +$100–$250 | Phase 2 only |
A CD4007UBE costs about $0.89 and contains a CMOS dual complementary pair plus inverter. It can be explored on the one-edge tile, but it is not the main-board recommendation: matching, body connections, and device operating region become the dominant uncertainty. Saving roughly $30 of matched-transistor cost on an eight-edge board is not worth sacrificing the experiment’s interpretability.
For the academic MVP, delete these entirely:
Keep or replace as follows:
| Original function | MVP replacement |
|---|---|
| MVM/crossbar | patchable reciprocal nonlinear resistor network |
| state integrators | natural RC/KCL state dynamics |
| sequential free/nudged phases | two continuously operating physical replicas |
| DAC nudge | OTA current injection |
| digital phase memory | simultaneous physical state comparison |
| outer-product update/programming | local capacitor charge/discharge |
| FPGA control | manual boundary selection and learn/freeze |
| ADC telemetry | buffered scope/DMM observation outside loop |
The cleanest paper is not merely “it learned.” It should isolate the choices that make the clockless implementation possible.
Proposed acceptance criteria, to be declared before network training:
Cw, update current, and state capacitance for at least 100× time-scale separation;A passive reciprocal network avoids the adjoint/transposed-Jacobian problem by construction, but it also excludes normal non-reciprocal attention. The transformer connection must therefore use tied, energy-based attention or be deferred to an active-adjoint phase.
It tests one scientific claim at a time. Every expensive item in the original plan exists to preserve a nearly complete transformer block. That is appropriate after the physical learning primitive is established, not before it.
The proposed sequence produces publishable intermediate results even if the final nonlinear task fails:
The main recommendation is therefore:
Build the
$70–$130one-edge tile, then the$170–$300eight-edge hybrid board. Do not purchase a CIM evaluation module, FPGA, DAC/ADC bank, or softmax hardware for the MVP.