[
 {
  "claim": "Analog/in-memory self-attention HARDWARE provably exists across multiple substrates, spanning real fabricated silicon to detailed simulation \u2014 directly answering GAP 1's core question. Fabricated: a UCSD 65nm CMOS charge-based SRAM-CIM attention accelerator (Moradifirouzabadi, Dodla, Kang; arXiv 2409.04940 / ESSERC 2024 / IEEE 10719540), the first to use charge-based analog CIM in SRAM for transformers, with measured 14.8 TOPS/W (analog core) and a custom 9-T bitcell doing the Q-dot-K^T score via capacitor charge-sharing. Simulated/architected: a Julich gain-cell (charge-based, capacitor) in-memory attention design (Leroux et al.; arXiv 2409.19315 / Nature Comp. Sci. 2025, s43588-025-00854-1) reporting ~70,000x energy / ~100x speedup vs GPU. Memristor/RRAM: a Nature Sci. Reports 2024 memristor self-attention accelerator (s41598-024-75021-z; 128x128 subarrays, 2-bit cells, NeuroSim/32nm) and the STAR RRAM softmax engine (arXiv 2401.17582, DATE 2023). Photonic: a cascaded TFLN-microring softmax proposal (arXiv 2603.12934, 2026).",
  "confidence": "high",
  "sources": [
   "https://arxiv.org/pdf/2409.04940",
   "https://arxiv.org/html/2409.04940v2",
   "https://arxiv.org/abs/2409.19315",
   "https://www.nature.com/articles/s41598-024-75021-z",
   "https://arxiv.org/pdf/2401.17582",
   "https://arxiv.org/pdf/2603.12934"
  ],
  "evidence": "Merges claims 0, 3, 16, 19, 5, 6. UCSD chip: 'The accelerator is fabricated in 65nm CMOS technology... first to use charge-based analog CIM in SRAM... for Transformer application' with measured 14.8 TOPS/W and a die photo \u2014 real silicon (claims 3, 16, all 3-0). Julich: 'custom self-attention in-memory computing architecture based on emerging charge-based memories called gain cells' (claim 0, 3-0). Nature Sci Reports memristor: 128x128 subarrays, 2-bit, Roff/Ron 1MOhm/100kOhm, NeuroSim V3.0 at 32nm (claim 19, 3-0). STAR is an RRAM softmax engine (claim 5, 3-0). All primary peer-reviewed sources, unanimous votes.",
  "vote": "consolidated 3-0 (claims 0,3,5,16,19); claim 6 photonic at 3-0"
 },
 {
  "claim": "EVERY surviving analog/in-memory attention implementation is INFERENCE-ONLY / fixed-weight \u2014 none performs in-situ training or on-device weight updates \u2014 so they fall in the large-but-fixed-weight inference camp, NOT the in-situ-trainable camp the EP demo requires. The Julich gain-cell design reaches GPT-2-comparable performance via OFFLINE hardware-aware initialization + offline backprop fine-tuning (~3,000 + ~10,000 iterations), all before deployment; gain cells store KV-cache ACTIVATIONS (token projections), not learned weights. This is the load-bearing limitation for an in-situ-EP demo: the analog-attention datapath is validated, but the trainability requirement is unmet by all named products/papers.",
  "confidence": "high",
  "sources": [
   "https://arxiv.org/abs/2409.19315",
   "https://arxiv.org/pdf/2409.19315v1",
   "https://arxiv.org/pdf/2409.04940"
  ],
  "evidence": "Claim 2 (3-0): 'initialization algorithm achieving text processing performance comparable to GPT-2 without training from scratch'; verifier confirmed weights computed offline/digitally, NO in-situ training, gain cells store KV-cache activations not weights, with ~13,000 offline fine-tuning iterations. Claim 12 (3-0) confirms the Julich design is SPICE-simulated (TSMC 28nm PDK), full floorplan/layout, but explicitly 'NOT physically fabricated' and 'limited to device simulations.' The UCSD chip (claims 3,4,16) is likewise an inference accelerator. Across all 20 claims, none asserts in-situ weight learning.",
  "vote": "3-0 (claims 2, 12)"
 },
 {
  "claim": "The softmax exponential + normalization IS physically realizable in analog in principle: a standard emitter-coupled (BJT) or subthreshold source-coupled (NMOS) differential-pair / winner-take-all network natively computes softmax, because KCL at the shared tail node makes each branch current = exp(x_i/V_T) / sum_k exp(x_k/V_T) \u2014 the normalization/division is obtained 'for free' from the shared-current node with NO explicit analog divider. The exponential I-V comes from subthreshold MOS (ID proportional to exp((Vgs-VTH)/nVT), tail currents kept small, ~180-300 nA) or BJT forward-active (any tail current). This is the classic Gilbert normalizer / translinear-principle result, independently corroborated across multiple sources.",
  "confidence": "high",
  "sources": [
   "https://arxiv.org/pdf/2305.13649",
   "https://arxiv.org/html/2507.04338v1"
  ],
  "evidence": "Merges claims 8, 9, 11. Claim 8 (3-0): 'IC,i = exp(xi/VT) / sum_k exp(xk/VT) * IEE'; KCL at shared emitter node yields the softmax denominator for free, no divider; verifier notes this is textbook Gilbert normalizer/translinear, independently corroborated (MDPI Electronics 2021 current-mode softmax). Claim 9 (3-0): subthreshold ID exponential, 180-300nA tested, BJT forward-active any tail current. Claim 11 (3-0): voltage-mode WTA branch current 'is identical to the softmax equation' (Zyarah & Kudithipudi arXiv 2507.04338, citing foundational Elfadel & Wyatt 1994). Caveats: NMOS exponent has slope factor n; only valid in weak inversion; real BJT breadboard shows +/-4.2% error.",
  "vote": "3-0 (claims 8, 9, 11)"
 },
 {
  "claim": "GAP 1(c) CONFIRMED \u2014 real analog-attention prototypes overwhelmingly adopt the pragmatic mixed-signal split: keep softmax/normalization (and often the value-multiply) in DIGITAL/LUT/CMOS, put only the linear maps + score dot-products in analog. Concrete instances: (a) UCSD 65nm chip computes only Q-dot-K^T in analog CIM (binary token-pruning decision via comparator), with softmax AND value-multiply done exclusively in the digital processor for the ~25% unpruned tokens; (b) the FeFET IMC approach (Julich ref [10] = Laguna et al., Frontiers in Electronics 2022) puts ONLY Q/K/V linear projections in analog, computing the attention dot-product in digital CMOS with K/V cached in SRAM; (c) the Nature Sci. Reports memristor accelerator maps only the linear MatMuls onto RRAM crossbars while softmax is done off-crossbar (RRAM compare-select for xmax + LUT/CMOS for exp/log); (d) STAR computes softmax exp via CAM+LUT lookup, not analog exp physics. NOTE the dissent: the Julich gain-cell paper itself does the OPPOSITE (computes attention in-memory) and replaces softmax with ReLU/HardSigmoid because softmax normalization needs a costly across-sequence vertical connection 'challenging to implement using analog circuitry.'",
  "confidence": "high",
  "sources": [
   "https://arxiv.org/pdf/2409.04940",
   "https://arxiv.org/pdf/2409.19315v1",
   "https://www.nature.com/articles/s41598-024-75021-z",
   "https://arxiv.org/pdf/2401.17582"
  ],
  "evidence": "Merges claims 4, 15, 18, 5, 13. Claim 4 (3-0): 'Softmax... and multiplying with value embeddings (V) are also performed in the digital processor only for the unpruned tokens'; 'No Softmax, normalization, or value multiplication occurs in the analog domain.' Claim 15 (3-0): FeFET ref [10] uses 'IMC only for computing the linear projections... attention itself is not computed in memory.' Claim 18 (3-0): memristor accelerator softmax 'divided into two parts: RRAM-based compare and select logics... and look-up tables for exponential and logarithmic functions.' Claim 5 (3-0): STAR uses CAM+LUT for exp, exploiting softmax precision-insensitivity. Claim 13 (3-0): Julich replaces softmax with ReLU because normalization 'necessitate[s] an additional vertical connection along the sequence dimension... challenging to implement using analog circuitry' \u2014 a concrete instance of the softmax-mapping difficulty.",
  "vote": "3-0 (claims 4, 5, 13, 15, 18)"
 },
 {
  "claim": "Photonic softmax for attention has been PROPOSED (not fabricated): a cascade of N tunable thin-film lithium niobate (TFLN) microring resonators synthesizes the per-channel exp(x_n - max) optically, with a single shared-WDM-laser PI feedback loop performing normalization, and electronic preprocessing (max-finding, shift/bias, digital interfacing) kept off-chip \u2014 itself a photonic instance of the GAP 1(c) split. Accuracy is depth/Q-limited: at the FDTD-validated quality factor (Q~10,300-15,500, Dmax~0.36) only N=5-7 rings are practical with error up to ~11%; sub-percent error (N~20-30) requires unrealized high-Q (Q>=1e6) devices. This is conceptual/layout + 3D-FDTD simulation only, not buy-now hardware.",
  "confidence": "medium",
  "sources": [
   "https://arxiv.org/pdf/2603.12934"
  ],
  "evidence": "Claim 6 (3-0): N=10 -> 2.68% error, N=20 -> 0.67%, N=30 -> 0.30% analytically, but FDTD regime supports only N=5-7 with ~11% error. Claim 7 (2-1, the only split vote): electronic max/shift/bias preprocessing, photonic exp + PI-feedback normalization; verifier flagged that summation is actually ELECTRICAL (Eq.35) and only normalization is photonic, and that TABLE VII labels the full softmax as 'Conceptual + layout' \u2014 simulation/proposal, not silicon. Single source (Park & Park, Chungnam National Univ., 2026); medium confidence due to one split vote and proposal-stage maturity.",
  "vote": "claim 6 at 3-0; claim 7 at 2-1 (split)"
 },
 {
  "claim": "PARTIAL GAP-3 signal (the only endurance/write-stress evidence in the surviving set): non-volatile memories (memristor/RRAM, Flash, FeFET, PCM) were explicitly rejected for in-memory KV-cache computation because each step must WRITE K/V values and NVM has slow writes, high write energy, and low endurance; charge-based gain cells were chosen specifically for higher endurance and lower write energy/time. This indirectly supports the EP-demo concern that write-limited NVM substrates are stressed by frequent updates \u2014 but NO surviving claim gives per-device endurance NUMBERS (cycles-to-failure), and ECRAM/electrochemical-RAM is NOT mentioned anywhere in the evidence.",
  "confidence": "high",
  "sources": [
   "https://arxiv.org/pdf/2409.19315v1"
  ],
  "evidence": "Claim 14 (3-0): 'Non-volatile memory technologies exhibit slow write speeds, high energy consumption during the writing process, and low endurance, which collectively limit their suitability for IMC of the attention mechanisms... gain cells have more endurance and require less write energy and time than non-volatile memories.' Verifier added independent context (not in primary claim): RRAM endurance ~1e6-1e9 cycles, PCM similar, vs charge-based/SRAM effectively >1e15 \u2014 but this is verifier background, not a separately voted claim. The reference [9] is Sebastian et al. Nature Nanotechnology 2020. This is the closest the evidence gets to GAP 3; it is directional, not a quantified endurance budget.",
  "vote": "3-0 (claim 14)"
 },
 {
  "claim": "Noise-margin quantification for an analog attention pipeline: a variation-aware memristor ViT accelerator simulation (MDPI Electronics 2026, 15(5),1116) reports tolerating ~35% analog computation error + ~10% memristor conductance variation while matching Top-1 accuracy of a digital baseline \u2014 useful for sizing how much analog imprecision an in-memory attention datapath can absorb. Caveats: it is simulation (not silicon), the match is a LARGER analog ViT-L vs a SMALLER digital ViT-B (not like-for-like), the '5nm baseline' is primarily the ENERGY comparator (not the accuracy one), and the paper is standard ViT inference (NOT energy-based/Hopfield attention and NOT Equilibrium Propagation).",
  "confidence": "medium",
  "sources": [
   "https://www.mdpi.com/2079-9292/15/5/1116"
  ],
  "evidence": "Claim 17 (3-0): 'up to 35% analog computation error and 10% memristor conductance variation, the analog ViT-L accelerator maintains Top-1 accuracy equivalent to that of a digital ViT-B.' Verifier flagged three qualifications (ViT-L vs ViT-B mismatch; 5nm baseline is energy comparator; no EP/energy-based attention). Single peer-reviewed source; the headline numbers are robust but the 'energy-based attention' framing is the claimant's interpretive bridge. Medium confidence: unanimous vote but single source and interpretive caveats.",
  "vote": "3-0 (claim 17)"
 },
 {
  "claim": "Sole datapoint relevant to GAP 1's full-analog-nonlinearity question: the analog-softmax-circuit author (Sillman, arXiv 2305.13649) argues an analog softmax block only pays off INSIDE a fully-analog system, because isolating it and bridging via ADC/DAC arrays would dwarf the processing block's power; he points to IBM's fully-analog NN-training hardware (PCM + capacitive-MOS matrix-multiply arrays) as the right integration context. This is a hedged single-author opinion (breadboard prototype) and argues AGAINST the GAP 1(c) digital-softmax split when the surrounding datapath is already analog \u2014 relevant nuance for an all-analog EP system.",
  "confidence": "medium",
  "sources": [
   "https://arxiv.org/pdf/2305.13649"
  ],
  "evidence": "Claim 10 (3-0): 'the amount of power the ADC and DAC arrays would consume... would also dwarf the power consumption of the processing block... this processor will likely find its home in a fully-analog design scheme. AI labs such as IBM have already begun redesigning neural network training hardware as fully analog systems by using phase-change memory (PCM) and capacitive MOS arrays.' Verifier notes this is a hedged opinion in a breadboard preprint and the IBM line is one motivational sentence. Medium confidence: unanimous vote but explicitly an opinion, not a measured result.",
  "vote": "3-0 (claim 10)"
 }
]