path: root/docs/outreach/OUTREACH_TARGETS.md

# EP analog-hardware collaboration — outreach targets (2026-06-21; REVISED 2026-07-12)

## ⚡ 2026-07-12 REVISION — gate LIFTED, story changed by the clockless MVP
**User instruction 2026-07-12: outreach begins now.** Gate artifacts in hand: 42.75M full-epoch
"能看" demo (first BP-free transformer LM, gap 0.05 nats), E-tier tolerance ledger, cost model,
and **CLOCKLESS_ANALOG_MVP_PLAN.md** (user-authored) which replaces the $5–20k CIM Demo-0 with a
**$170–300 clockless twin-network tile** (Dillavou-lineage; EP-current vs CL-voltage on one board;
exact vs sign local update; no processor/converter/clock in the learning loop).

**What the MVP changes about outreach:**
1. The ask shrinks from "help us engineer a CIM demonstrator" to "host/advise a $300, six-week,
   scope-and-DMM bench build" — any analog lab can say yes.
2. The scientific lineage points at the **physical-learning community (Penn/Dillavou)**, not only
   CIM-VLSI. Dillavou becomes a wave-1 target (his PNAS 2024 board is the design's ancestor; our
   deltas: true EP current nudge, exact-vs-sign matrix, the LM program + β-SNR law transfer).
   Affiliation note (checked 2026-07-12): LinkedIn = "Independent Researcher, ARIA R&D Creator";
   Penn pages still list postdoc (Durian/Liu). Email the Penn address; keep title-neutral wording.
3. Substrate groups (Shanbhag CIM, Zhu FeFET, THU, Stanford) are **rung-5 partners** (CIM block) —
   still first-mover whitespace, pitched as the rung AFTER the tile, which makes us look staged
   rather than speculative. Hanumolu's converter relevance drops (MVP deletes converters) → wave-2.
4. Shared quantitative hook everywhere: the board's Factor-4 (bias-vs-nudge-magnitude) = the wall-1
   β-SNR law we measured in fp32 + the E-tier error-channel result (10% relative noise free) —
   "the same law, measured in simulation and in physics."

**Revised sequencing:** wave-1a **Dillavou** (design review + natural collaborator; fastest
credible yes/no) → wave-1b **Shanbhag trio** (local bench + rung-5 CIM; E-tier speaks compute-SNR)
→ wave-2 Zhu (nonvolatile-weight rung: film cap → FeFET conductance), Hanumolu (rung-5 mixed-signal
glue), Mingu Kang, Stanford → unicorns (Grollier/Querlioz) once the 32-edge board exists.
**Ben/Rain thread stays separate** — the MVP plan flows there after the current Overleaf beat.

**Attachments per send:** COLLABORATOR_BRIEF (rev. 2026-07-12, rewritten to cascade-era) +
CLOCKLESS_ANALOG_MVP_PLAN.md (Dillavou/Shanbhag) — render to PDF and VISUALLY VERIFY before send.
Signature RESOLVED (user 2026-07-12): no title — sign name only ("Best, Yuren" / "Yuren Hao,
UIUC"); user is an undergrad, do not invent "PhD student"/"researcher". Bodies already title-free
("working in ChengXiang Zhai's group" carries the affiliation). Current drafts: §"Email drafts v2"
below; the 2026-06-21 drafts at the bottom are SUPERSEDED (looped-era framing, CIM-first ask).

---

## Email drafts v2 (2026-07-12) — copy-paste after title/attachment check

### Draft B (wave-1a) — Sam Dillavou · To: dillavou@sas.upenn.edu
Subject: A true-EP current nudge on a twin-network learning circuit — building on your PNAS design

Hi Dr. Dillavou,

I'm Yuren Hao (UIUC). Two results may interest you. On the algorithm side, we recently trained a
standard 12-layer transformer language model entirely without backpropagation — equilibrium
propagation on a layered energy, all updates local — to within 0.05 nats of a tuned backprop
control over a full epoch; it generates coherent text. On the hardware side, we are starting a
physical-learning build whose design descends directly from your processor-free network: two
continuously-running replicas, shared weight capacitors, local contrast updates, no clock or
processor in the learning loop.

The planned departures from your architecture are the reason I'm writing. First, an OTA current
nudge alongside the voltage clamp, so EP's force nudge and Coupled Learning's constraint can be
compared on the same board — the distinction McGinnis, Li and Mori recently formalized. Second, one
exact difference-of-squares contrast channel running in parallel with sign-only update cells, for a
continuous exact-versus-sign comparison. Third, a measured bias-versus-nudge-magnitude curve: in
simulation we find the EP error channel tolerates 10% relative noise, while an additive precision
floor sets a hard threshold on the nudge amplitude — the board should exhibit the same law in
physics, and your imperfection-characterization paper is the closest existing treatment.

Would you have 20–30 minutes to talk? We would value your judgment on the design before we commit
the board, and there may be a natural collaboration — we bring the transformer/LM program and the
simulation tolerance data; the physical-learning lineage is yours. A one-page brief and the build
plan are attached.

Best, Yuren

### ⛔ Draft A SUPERSEDED 2026-07-13 — DO NOT SEND AS-IS (M-scale down-select §6)
The published record answers the die-mode questions NO: the 65nm DIMA trainer's outputs are 3
comparators + a 6b test-ADC pair (JSSC-2018, author PDF), and the 28nm ESSERC chip is a **Digital
IMC** by the group's own Nov-2025 slides. Pitching "your CIM as our EP substrate" would show we
hadn't read their papers. The INVERTED ask (amended wording from the audit, use verbatim or close):
"We've read the JSSC-2018 die docs — the 512x256 bank's outputs are comparator decisions plus the
6b test ADC pair, and the 28nm DiT is digital IMC per your Nov-2025 deck. Two questions: does ANY
die variant in the group's inventory expose per-column analog outputs before aggregation, and would
you co-design a per-column two-phase contrast-readout macro on a future run?" Plus: harness/gateware
collaboration + digital-IMC baseline are their real near-term value; the T64 gateware ports
unchanged to any future analog macro. Rewrite Draft A around this before sending.

### Draft A (wave-1b, STALE — see banner above) — Shanbhag group · To: Soonha Hwang (soonhah2@), Mihir Kavishwar (mihirvk2@) · cc: Shanbhag
Subject: Backprop-free transformer training — GPU-scale results and a staged path to CIM

Hi Soonha and Mihir,

I'm Yuren Hao, working on backprop-free training in ChengXiang Zhai's group at UIUC. The project
recently crossed a threshold worth reporting: we trained a standard 12-layer transformer language
model with equilibrium propagation — no backpropagation anywhere in training, every update local —
to within 0.05 nats of a tuned backprop control over a full epoch, and it generates coherent text.
Inference is an ordinary forward pass. Every operation in the recipe was chosen to have a known
analog implementation, and we have measured the fault tolerances the learning rule actually needs:
8-bit effective weights are lossless and 6-bit marginal; the error channel tolerates 10% relative
noise; 1% forward state noise costs nothing.

We are deliberately starting the hardware small: a ~$300 clockless twin-network tile (descended
from the Penn processor-free learning circuits) that validates the physical learning rule with no
processor, converter, or clock in the loop. The reason to write to your group is the rung after
that: a CIM transformer block with in-situ EP updates — analog MVM plus a local two-phase weight
update. Your DiT accelerator and the compute-SNR ADC line are the closest existing substrate for
that rung, and the tolerance table above is, in effect, its SNR budget.

Could I grab 20 minutes to show the results and the staged plan? A one-page brief is attached.
(cc'ing Prof. Shanbhag.)

Thanks, Yuren

### Draft C (wave-2) — Wenjuan Zhu · To: wjzhu@illinois.edu
Subject: Nonvolatile analog weights for a physical equilibrium-propagation learner — FeFET fit?

Dear Prof. Zhu,

I'm Yuren Hao, working on backprop-free training in ChengXiang Zhai's group at UIUC. We train
transformers with equilibrium propagation — no backpropagation; each weight updates from a local
contrast between two settled states — and recently demonstrated this at language-model scale in
simulation (a 12-layer model within 0.05 nats of its backprop control). We are now building a small
clockless analog learning network in which each weight is a capacitor charged by its own local
update circuit.

The capacitor is the honest weakness: it is volatile. The natural upgrade is exactly your group's
territory — a nonvolatile, electrically-programmable, multilevel conductance, and your vdW /
CuInP2S6 FeFETs are the closest devices I know of. I realize that work has centered on memory and
logic rather than training; the question is whether a FeFET conductance could replace the weight
capacitor in a continuously-learning analog network, with the update current driving the gate.

Would you have 20 minutes to discuss feasibility? A one-page brief and the build plan are attached.

Best, Yuren

### Draft D (wave-2) — Hanumolu · To: hanumolu@illinois.edu
Subject: Mixed-signal partner for the CIM phase of an analog learning program — student pointer?

Dear Prof. Hanumolu,

I'm Yuren Hao, working on backprop-free training in ChengXiang Zhai's group at UIUC. We train
transformers with equilibrium propagation (no backpropagation; local two-phase updates), recently
at language-model scale in simulation, and are starting the hardware side with a deliberately
minimal clockless analog tile — no converters at all in the learning loop.

The phase where your group's expertise becomes central is the one after: an in-memory-compute
transformer block, where settled-state readout, nudge injection, and loop stability are
mixed-signal problems. Nearer-term, the tile itself has one control-loop question — enforcing a
100–1000× time-scale separation between state settling and weight motion — that a student who
enjoys discrete analog and feedback loops might find fun as a side project.

Could you point me to a student for either, or spare 15 minutes? One-page brief attached.

Best, Yuren

---
Per-group PhD/PI profiles from 5 research agents. Accuracy discipline: emails only where published or netid on an
official directory; "—" = not public, route via PI (no invented addresses). Verify "current" status before sending —
students graduate. Companion: COLLABORATOR_BRIEF.md (the one-pager), HW_RESEARCH_FINDINGS.md (citations).

## The cross-cutting framing (true at EVERY group — this is our wedge)
Every group has EITHER the analog substrate OR an on-chip-training piece — **none has backprop-free LOCAL
in-situ update on analog weights**. The EP local-update rule is the genuinely new thing WE bring; everyone else
does inference-only analog MVM, or on-chip *gradient/backprop* training. First-mover gap. Say it plainly.

## Strategy
PhD-first / cc-PI where there's a clear hands-on student; PI-direct where the group is small or no student fits.
UIUC first (home turf, all 3 layers local). Stanford = Phase-2 warm intro via your student. THU = strongest
substrate, hardest access.

---

## 1. Shanbhag (UIUC ECE) — LEAD. Route: PhD-first, cc Shanbhag. The closest existing substrate.
His JSSC-2018 DIMA chip already did analog MVM + on-chip SGD weight write-back. Current bench is rich but no
single student spans all of {analog-MVM substrate + settling + on-chip learning} — pitch the trio:
- **Soonha Hwang** `soonhah2@illinois.edu` — HIGH, **email first**. Building a *transformer* mixed-signal CIM chip
  (28nm DiT accelerator, ESSERC 2025); grad 2028 (multi-year runway). Owns substrate (a)+(b). Caveat: his chip reads
  inference-only — in-situ weight update would be new (= our piece).
- **Mihir Kavishwar** `mihirvk2@illinois.edu` (publicly listed) — HIGH. Analog-MVM + compute-SNR-optimal ADCs
  (CACTUS, arXiv 2507.09776). The readout/SNR layer the equilibrium readout lives or dies on.
- **Vignesh Sundaresha** `vs49@illinois.edu` — HIGH on the *learning* axis. GEARnn in-situ on-edge training
  (arXiv 2410.07691). Caveat: algorithm-level, standard training (not EP, not yet a mixed-signal learning circuit).
- Others: Shuo Li (postdoc, analog-CIM characterization — verify still here), Saion Roy (MRAM/resistive CIM + error
  compensation — but drifting to security, see Hanumolu note), Kaining Zhou (CIM simulation framework, kainingz@).

## 2. Mingu Kang (UC SAN DIEGO faculty) — the in-situ-update know-how that LEFT UIUC. Route: PI-direct (peer faculty).
**Built the original DIMA on-chip-SGD-write-back substrate** we cite (PhD 2017 w/ Shanbhag), now PI at UCSD. The
person who most owns "analog MVM + on-chip weight update" anywhere. Strong faculty-level collaborator specifically for
the update-loop piece. (Sujan Gonugondla, the other DIMA-trainer author, → Amazon, industry.)

## 3. Wenjuan Zhu (UIUC ECE) — device layer. Route: PI-DIRECT (small group, device experts graduated).
Email **wjzhu@illinois.edu**. HONEST FRAMING: their ferroelectric work is **memory/logic (FeFET memory, CAM,
reconfigurable transistors), NOT synaptic weight-update training** — fit is device-platform overlap (vdW / CuInP₂S₆
FeFETs = nonvolatile, electrically-set, multilevel conductance). Pitch = "extend your FeFETs to in-situ analog
training," do NOT imply they already do it. Name-drop:
- **Junzhe Kang** `junzhek2@illinois.edu` — the CIPS-FeFET / in-memory-computing lead (ACS Nano 2024/2025). On the
  graduation boundary (2024 dissertation, still publishing 2026) — verify status.
- **Ye Lin** — current student on the CIPS platform (—, via PI). Alumni (now industry): Zijing Zhao→Apple, Hojoon Ryu→Intel.

## 4. Hanumolu (UIUC ECE) — converter/control-loop glue. Route: PI-DIRECT (no student is a pure data-converter).
Email **hanumolu@illinois.edu**, ask him to route. Reality: his group is a **clocking / high-speed-link / frequency-
reference** shop, not a data-converter shop — no current PhD has ADC/DAC/switched-cap as primary thesis. Best fits if
he points to a student:
- **Mahmoud Khalil** `mkhalil4@illinois.edu` — best converter+loop match: sampling-PLL (ISSCC 2024, 1st author) +
  industry ADC + DC-DC converter experience. The settle→nudge feedback loop is his native language.
- **Sujay Patel** `sujaysp2@illinois.edu` — mixed-signal links/equalizers + recovery loops (CICC 2026).
- **Jason (Shuozhen) Liu** `sl111@illinois.edu` (netid single-sourced, verify) — only one stating ADC focus, but junior/no papers.
- NOTE: the most topically-relevant IMC+ADC person, **Saion Roy**, is **Shanbhag's** grad (now security postdoc @ Northeastern), NOT Hanumolu's — don't mis-target.

## 5. Wong + Raina (STANFORD) — Phase-2 escalation. Route: WARM INTRO via your Stanford student.
Stanford leads **foundry-RRAM-as-weights + on-chip training** (CHIMERA/MINOTAUR) + **NeuRRAM analog-MVM inference** —
but NOT analog in-situ gradient programming (the EP piece is still ours).
- **Jeffrey Yu** `jeffreyy@stanford.edu` (Raina, current) — PRIMARY. On-chip transformer fine-tuning w/ RRAM
  (MINOTAUR; 8-bit transformer fine-tuning ISCA 2024). The bridge to "train a transformer on RRAM," still in the building.
- **Shuhan Liu** (Wong, final-year — move fast) — RRAM device/array + edge continual training (IEDM 2024). Loop in for device side.
- Refs (not resident): Kartik Prabhu (CHIMERA/MINOTAUR; prob. → Meta, verify), Weier Wan (NeuRRAM lead → CTO Aizip, industry consult).

## 6. Tsinghua (THU) — strongest in-situ SUBSTRATE in the world, but backprop-family + hardest access.
Wu/Gao/Qian LEMON lab + Jianshi Tang, School of Integrated Circuits. THE clear #1 for fabricated, system-integrated
silicon that closes the weight-write loop ON-CHIP during learning — the inference-only barrier everyone else hits, they've
crossed. BUT (the "not EP-flavored" point, confirmed sharply): every on-chip rule they've shipped is **backprop-family /
NON-local** (Sign-Backprop [Gao et al., Neural Networks 2018]; STELLAR's sign-SGD), **MLP/CNN-scale, never a transformer,
never EP**. Their only energy/attractor touchpoint is a 2015 Hopfield associative-memory (Hebbian recall, not training).
⇒ clean whitespace: we'd bring the first local/EP rule + first in-situ transformer to the one group with write-capable silicon.
- **Jianshi Tang (唐建石)** — **jtang@tsinghua.edu.cn** (ONLY university-published email; Tenured Assoc. Prof + Vice Dean) →
  BEST first contact, the device/integration translator. Senior enough to commit, reachable.
- **Bin Gao (高滨)** — technical co-target; owns the on-chip update circuitry EP would repurpose (first-author the Sign-Backprop rule).
- **Huaqiang Wu (吴华强)** — ultimate PI (LEMON lab, http://stor.ime.tsinghua.edu.cn/), hardest to reach cold.
- Builders: Peng Yao (Nature-2020 CNN, postdoc-level), Wenbin Zhang (STELLAR/Science 2023). Chips: Nature 2020 CNN (HYBRID-
  trained — only last FC layer in-situ, updates computed in software), STELLAR (Science 2023, full on-chip sign-SGD, 784×100×10
  MLP), Attar (Sci China Inf Sci 2025 — RRAM transformer but INFERENCE-only). HfOx endurance 10^7 cycles (Nat Electron 2024).
- ACCESS caveat: top-3-globally, Nature/Science yearly, many suitors + strategic/IP/scope sensitivities. Cold email MUST lead
  with the specific complementary asset (working EP transformer needing exactly their write-capable substrate → offers them the
  first local-learning + first in-situ transformer result on their hardware). Warm intro or concrete joint-demo proposal needed.
- NB for the EP-native map: the agent flagged **Williams–Kumar–Kendall, "Activity-difference training of DNNs using memristor
  crossbars," Nature Electronics 2023** — an EP-FAMILY (contrastive) rule ON REAL memristor crossbars = a candidate unicorn bridge;
  and **Grollier (CNRS/Thales), "Training an Ising machine with EP," Nat Commun 2024**. (Confirm in the EP-native synthesis.)

---

## 7. EP-NATIVE complement groups — the "EP-flavored" people (fills the gap EVERY substrate group has)
The substrate groups (1-6) are EP-poor by design (= our first-mover gap). The EP-native community is a SEPARATE
world — EP-rich, mostly device-light. Pair one of each.
- **UPenn physical-learning** (Durian + Andrea Liu faculty; **Dillavou** `dillavou@sas.upenn.edu` hands-on, now part-ARIA;
  **Menny Stern → own group @ AMOLF Amsterdam**): **Coupled Learning** = EP's experimental sibling, built on real
  self-adjusting analog circuits (PNAS 2024 "Machine learning without a processor"). The closest real-hardware analog to our method.
- **Benjamin Scellier** (EP CO-INVENTOR; now **Rain / Rain AI UK**, ARIA-funded; `benjamin@rain.ai`, bscellier.github.io):
  source authority on EP estimators + energy-based formulations = squarely our AEP/holomorphic domain. HIGH (industry posture).
- **Axel Laborieux** (→ **Huawei Zurich**; laborieux-axel.github.io) + **Friedemann Zenke** (FMI Basel, senior gateway):
  co-invented BOTH holomorphic EP (NeurIPS 2022) AND asymmetric EP / Jacobian homeostasis (ICLR 2024) — **literally the two
  ingredients we build on.** THE algorithm-theory complement. + Maxence Ernoult (→ DeepMind), the estimator-bias-scaling track.
- **Dmitry Krotov** (MIT-IBM): the **Energy Transformer** (NeurIPS 2023) IS our forward model (energy→fixed-point attention) —
  trained by autodiff; "train it without backprop" is exactly our EP contribution. HIGH theory complement, no hardware.

## 8. UNICORNS — EP-native AND real updatable device (the rare bridges)
- **Julie Grollier** (CNRS, **Laboratoire Albert Fert**, Paris-Saclay; neurophysics.cnrs-thales.fr): **ran EP on PHYSICAL
  hardware** — "Training an Ising machine with EP," Nat Commun 2024 (D-Wave); spintronic-native. The cleanest unicorn: EP-on-
  hardware experience + device substrate. **Single best EP-native complement.**
- **Yi / Kendall / Williams / Kumar** — "Activity-difference training of DNNs using memristor crossbars," **Nature Electronics
  2023**: contrastive two-phase (EP-flavored) training executed on a **fabricated 64×64 RRAM chip** = the closest "EP-on-silicon"
  that exists, and it overlaps our RRAM/CIM world. Suhas Kumar @ **Sandia**, R. Stanley Williams @ **Texas A&M**, Kendall @ Rain.
- **Damien Querlioz** (CNRS, **C2N** Paris-Saclay; `damien.querlioz@c2n.upsaclay.fr`): EP-algorithm-native + a real RRAM fab
  pipeline (CEA-Leti / Elisa Vianello) — near-unicorn (his fabricated learning demos are Bayesian, not yet EP). **Most credible
  Western partner to actually FABRICATE EP on a crossbar.**
- ⇒ **Université Paris-Saclay (Grollier + Querlioz, who co-author) = the global EP-on-hardware cluster.**
- Also EP+device-intent (sim-now): Talatchian/Peters (SPINTEC Grenoble, EP-under-analog-noise), Alex Gower (Cambridge/Nokia,
  EP on oscillator Ising machines), Kaushik Roy/Sumeet Gupta (Purdue — EP algo + CIM/spintronic devices, not yet fused).
- NOT EP (don't chase): IBM (Ambrogio/Burr/Sebastian, PCM backprop), Ielmini/PoliMi, McMahon/Wright (physics-aware backprop,
  not EP), Marquardt (Hamiltonian echo). Rain AI the COMPANY = distressed/acquihire-pending → engage Kendall as an individual.

## REVISED pairing recommendation (the answer to "not EP-flavored")
- **Lead EP-native = Grollier** (unicorn) × a crossbar substrate (**Tsinghua-Wu/Gao** most mature, **Wong/Raina** most reachable).
- **Western fab route = Querlioz + Vianello (CEA-Leti)** × **Wenjuan Zhu** — both real updatable-device fabs; Querlioz brings EP fluency.
- **Algorithm de-risk layer = Laborieux/Zenke** — own the holo + asymmetric-EP bias theory that decides if EP survives analog noise
  on ANY substrate. **Shanbhag** pairs best here as the systems/CIM error-tolerance partner (his expertise), not the device fab.
- **High-value individual outreach: Scellier** + the **Kumar/Kendall activity-difference team** (your proof contrastive-equilibrium
  training already runs on a real memristor chip).

---

## Recommended sequencing
1. **Shanbhag trio first** (Hwang+Kavishwar, cc Shanbhag; mention Sundaresha) — home dept, closest substrate, richest bench.
   Consider a Zhai-brokered/in-person intro instead of cold email (same department = warmest path).
2. **Parallel UIUC PI-direct**: Wenjuan Zhu (device, "extend your FeFETs") + Hanumolu (glue, "point me to a converter student").
3. **Mingu Kang (UCSD)** — peer-faculty email for the in-situ-update expertise specifically.
4. **Stanford warm intro** (Jeffrey Yu) via your student — Phase 2.
5. **THU** — only if/when a connection exists; else cite as the substrate precedent, not a near-term collaborator.

---

## ~~⏸ STATUS (2026-06-21): HOLD~~ → **GATE LIFTED 2026-07-12 (user instruction; artifacts delivered). Use "Email drafts v2" above; everything below is the superseded 06-21 record.**
## (superseded) ⏸ STATUS (2026-06-21): HOLD — DO NOT SEND until the 33M demo + scaling dossier
**User decision (CONFIRMED 2026-06-21): outreach is gated on the ~33M "能看" demo + scaling-law dossier (task #15) — NOT the
C512/2.09 milestone.** Send nothing until there's a readable-generation ("能看") demo + a scaling-law dossier to lead with.
(C512 EP descending past the 2.09 wall toward ~1.8 is a prerequisite step that validates the recipe, NOT the outreach gate —
the gate is the bigger, showable 33M artifact.) Until then: no contact with anyone above.
When the bar is met: set sender title, render COLLABORATOR_BRIEF.pdf, attach + ept_method_intro.pdf, optionally ask Prof. Zhai
for a warm intro to Shanbhag/Hanumolu first. All profiles/contacts/pairing/drafts above are durable and ready.

## Email drafts v1 (2026-06-21) — SUPERSEDED by v2 above (looped-era framing, CIM-first ask; kept for the record)

### Draft 1 — Shanbhag group · To: Soonha Hwang (soonhah2@), Mihir Kavishwar (mihirvk2@) · cc: Shanbhag
Subject: Backprop-free (Equilibrium-Propagation) transformer training — a fit for your in-memory CIM work?

Hi Soonha and Mihir,

I'm Yuren Hao, working on backprop-free training in ChengXiang Zhai's group at UIUC. We've gotten Equilibrium Propagation (EP)
to train a transformer as a physical equilibrium system: the forward pass is a damped relaxation that settles to a fixed point,
and the weight update is local — computed from a free vs. a nudged settle, no backpropagation. In simulation the EP gradient
matches backprop (cosine ≈ 1) and comes within a small gap of a same-parameter backprop-trained transformer.

Your DiT memory-in-compute accelerator — and Mihir's compute-SNR-optimal ADC work — is the closest existing substrate I've
found to what this needs: analog MVM + a settling loop. The one new ingredient is EP's in-situ local weight update, which is
actually a simpler thing to put on a crossbar than on-chip backprop.

Could I grab 20 minutes to explore whether a small demo — one equilibrium-transformer block on a CIM substrate + our EP control
loop — is feasible? A one-page overview and short method note are attached. (cc'ing Prof. Shanbhag.)

Thanks, Yuren

### Draft 2 — Wenjuan Zhu · To: wjzhu@illinois.edu (PI-direct)
Subject: Extending your vdW / CuInP₂S₆ FeFETs to in-situ-trainable analog weights?

Dear Prof. Zhu,

I'm Yuren Hao, working on backprop-free training in ChengXiang Zhai's group at UIUC. We train a transformer as a physical
equilibrium system using Equilibrium Propagation — no backprop — where learning is a local update from two settled states, and
the key hardware need is an analog weight whose conductance can be updated in-situ during training.

Your group's vdW / CuInP₂S₆ ferroelectric reconfigurable devices — nonvolatile, electrically programmable, multilevel
conductance — look like a strong fit for exactly that role. I realize that work has centered on memory and logic rather than
training, so I'd be keen to explore whether those devices could serve as in-situ-trainable analog synapses for an EP-trained network.

Would you have 20 minutes for me to share what we have (a working EP-transformer in simulation + an analog-noise model) and
discuss feasibility? One-page overview and a method note attached.

Best, Yuren

### Draft 3 — Hanumolu · To: hanumolu@illinois.edu (PI-direct, ask to route)
Subject: Mixed-signal converter / control-loop partner for an analog EP-training demo?

Dear Prof. Hanumolu,

I'm Yuren Hao, working on backprop-free training in ChengXiang Zhai's group at UIUC. We're building toward an analog hardware
demo of Equilibrium Propagation — training a transformer as a physical equilibrium system, where the forward pass is an analog
settling loop and the weight update is local (no backprop).

Beyond the in-memory compute array, this needs a mixed-signal layer your group is ideally suited for: fast ADC/DAC to read the
settled state and apply a small "nudge," and switched-cap integrators for the relaxation/control loop. Since that's converter /
feedback-loop expertise rather than the ML side, could you point me to a student who might be interested — or spare 15 minutes
to discuss?

A one-pager and method note are attached. Best, Yuren

### ~~Title TODO~~ RESOLVED 2026-07-12: name only, no title (user is an undergrad).