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# hw_sim ledger
## v0 (cell_v0.py, 2026-07-17): behavioral sanity
- 64-branch settle 1.14 us with ASSUMED 60 pF node — later shown ~100x optimistic.
- Two-phase offset rejection x376 (5 mV Vos).
## v1 (cell_v1.py, 2026-07-17): datasheet-anchored — FIRST REAL DESIGN VERDICT
Anchors: AD7528 R=11k typ, R_eq(code) 0.8R-2R, C_OUT 50-120 pF/chip, settling 350/400 ns
(the chip is never the bottleneck); MCP6022 GBW 10 MHz, Vos max 500 uV.
KEY PHYSICS: 64 OUT pins share the column bus -> C_bus = 64 x ~85 pF = 5.4 nF.
E1 (settle, commit <=3 us / kill >7 us):
naive (R_f=10k, no comp) 16.6 us KILLED
R_f=10k + C_f 93 pF 8.2 us killed
R_f=3k + C_f 170 pF 5.3 us survives kill, misses commit
R_f=1k + C_f 294 pF 3.14 us 5% over commit — borderline
E2 at (1k, 294pF): Vos 500 uV -> single-read 2.71 mV, two-phase differential 0.88 uV
= x3088 rejection, 100x under the 0.1 mV contrast floor. Offset story SOLID.
DESIGN OPTIONS to clear the commit gate (for Dillavou session):
(a) faster TIA: GBW 50 MHz class (e.g. OPA356/OPA2356 ~$1-2) -> projected ~1.4 us;
(b) bus segmentation: 2x32 loads, two TIAs, digital sum -> C_bus/2 -> ~2.2 us at 10 MHz;
(c) accept 3.14 us: wall-clock 9-14 d -> ~5% slip, not a cliff.
NEXT (v1.1): resistor-mismatch Monte Carlo -> ENOB-after-cal proxy; op-amp noise integration
vs contrast floor; then stage C = SPICE-in-the-loop EP training (8x8 toy).
## OPEN QUESTION FOR THE DILLAVOU SESSION (user-parked, 2026-07-17)
Bus-capacitance settle (the v1 finding): naive 64-on-one-bus = 5.4 nF -> 16.6 us (killed).
Candidate fixes to put to the experts, in our preference order:
(b) bus segmentation 2x32 + dual TIA, digital sum (~2.2 us, no new parts) — current favorite;
(a) faster TIA (OPA356-class 50 MHz, $1-2) (~1.4 us);
(user idea) time-multiplexed bucket rotation with discharge/precharge phases — maps to real
segmented-bus + precharge techniques; feasibility/complexity tradeoff = expert question;
(c) accept 3.14 us (5% schedule slip).
None of this blocks the sim line: v1.1 (mismatch MC / ENOB, noise integration) and stage C
(SPICE-in-the-loop toy training) proceed independently of which fix wins.
## v1.1 (cell_v11.py, 2026-07-17): ENOB Monte Carlo + noise budget
A. Per-BIT ladder mismatch MC (sigma_bit 0.4% ~ datasheet +-1 LSB class), per-cell single-scale
cal: **ENOB 8.51 b mean, p5 8.34 b — clears the 7.0 screen bar with margin.** The Y3 gray-
market screen is realistic. (First model iteration with Thevenin-only structure was vacuous —
single-scale cal cancelled it exactly; per-bit structure is the honest model.)
B. Noise budget at (R_f=1k, C_f=294pF): op-amp 8.7 nV/rtHz x noise-gain peak x16 over the
closed-loop band -> **138.7 uV RMS output-referred vs the 0.1 mV contrast floor = 0.7x
headroom, MARGINAL.** This is hardware wall-1 with a SPICE number: the contrast signal
scales with beta while this floor is fixed -> the machine WANTS big nudges — exactly what
the GPU campaign independently concluded (ride-high beta recipes). Mitigations if more
headroom needed: post-settle integration window (1/sqrt(T)), read averaging, band-limit
after settle, larger VREF. Model caveats: flat op-amp noise only (no 1/f, no Johnson/DAC
switch terms — order-checked small at this impedance level).
## Stage C (toy_loop.py, 2026-07-17): SPICE-IN-THE-LOOP TRAINING — LADDER CERTIFIED
8 -> 8 tanh -> 4 toy net; EVERY MVM (forward + transpose error transport) solved by ngspice on
differential resistive columns with: per-bit ladder mismatch (fixed device), per-column offsets,
8-bit code quantization of an fp32 digital master (T64 word-streaming), and the v1.1-measured
139 uV read noise. 7,200 DC solves in 26 s.
| arm | final CE | train acc |
|---|---|---|
| ideal numpy | 0.0211 | 100% |
| behavioral non-idealities | 0.0213 | 100% |
| **SPICE-in-the-loop** | **0.0213** | **100%** |
- SPICE == behavioral to the 4th decimal in a TRAINING context => the behavioral abstraction
(exactly what the GPU trainer's fault-injection flags implement at 72M) carries circuit
authority. The fidelity ladder [SPICE constants -> behavioral at scale] is certified.
- Training THROUGH the circuit is indistinguishable from ideal at this scale — the "gradient
from a simulated circuit" convergence-curve artifact exists before any soldering.
- Session-ready claim: "we trained a network where every matrix product, including the
transpose reads, ran through a SPICE model of the exact parts on the BOM."
NEXT candidates (autonomy line): scale toy to 32x32 (overnight class); add settle-transient
into the loop (replace DC solves at the found (R_f,C_f) point) to couple timing and training;
port the ride/beta story onto the circuit noise floor (nudge amplitude sweep vs 139 uV).
## Energy ledger (energy_ledger.py, 2026-07-17): SPICE core + datasheet periphery vs digital
SPICE-measured analog network core: 2.87 pJ/MAC (resistive burn over the 4.2 us discrete dwell).
| scenario | pJ/MAC (wiring 1-3x band) | vs digital INT8 system 0.3-1 pJ/MAC |
|---|---|---|
| MVP discrete parts | 487-1462 | loses ~1000x (op-amp quiescent x long dwell + discrete ADC) |
| T64 word-streaming | 587-1562 | loses ~1000x (+ reload/DRAM tax) |
| Integrated weight-stationary (coherent: C/100 -> 100 ns dwell) | 0.21-0.63 | **0.5x-4.8x: parity to ~5x win, ADC-dominated** |
HONEST CONCLUSIONS:
1. The boards (MVP/T64) are trainability demos, never efficiency demos — say it before referees do.
2. The integrated projection at 8-bit lands at PARITY-TO-5x, not the 10-100x of CIM marketing;
the residual is the ADC tax. Paths beyond: fewer/narrower reads, analog inter-layer
accumulation, low-precision contrast reads.
3. EP's energy contribution is CATEGORICAL, not per-MAC: it makes TRAINING possible on analog
fabric at all (inference-only CIM can't train; digital training is the displaced baseline).
4. Method: analog side SPICE-measured (+-2-3x wiring band), digital side literature constants
(Horowitz/H100 envelope) — the standard comparison protocol, uncertainty stated.
## FAB STRATEGY (plan of record, 2026-07-18, user-aligned)
JLC PCB + SMT assembly for everything; SOCKET the screened gray-market MDACs (DIP/PLCC sockets)
— machine quality + swappability/debuggability for the risky parts. Design-for-test in layout:
test points, jumpers, isolatable single-column bring-up region (first board runs Stage-1 gates
on one column). First-article batch of 5 before volume. Hand-soldering is not an option at T64
scale (2,250 x 20 pins); even the $300 MVP goes JLC economy so identical boards can ship to
Sam Dillavou's lab. Toolchain endpoint: SKiDL -> KiCad -> scripted Gerber+BOM+CPL = JLC-ready order
package from the same simulated source. SPICE pre-verification (v0/v1/v1.1/Stage-C) exists to
hold respins to 1-2 x 1-2 weeks. Bonus: machine-assembled layout parasitics are REPRODUCIBLE,
narrowing the 1-3x wiring band in the settle/energy ledgers.
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