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diff --git a/THREE_PART_EVIDENCE.md b/THREE_PART_EVIDENCE.md index 725753d..01a738b 100644 --- a/THREE_PART_EVIDENCE.md +++ b/THREE_PART_EVIDENCE.md @@ -153,6 +153,23 @@ The hardware claim is: the full update is simulated with published device equations and nonideal local sampling, and its primitive sample/subtract path has a SPICE check. A fabricated-chip demonstration remains future work. +## Closest hardware-correction methods + +[Dillavou et al. (2025)](https://arxiv.org/abs/2505.22887) identify biased +local updates in a physical CLLN and introduce overclamping. Their appendix +describes each edge's actual bias as an unknown deterministic function of +system state, while their tractable dynamics use a fixed bias vector. This is +the direct experimental problem behind the state-dependent ladder. + +[Wu et al. (2025)](https://arxiv.org/abs/2502.06309) and +[Xiao et al. (2026)](https://arxiv.org/abs/2602.21321) correct asymmetric +conductance updates in analog in-memory SGD using residual arrays or dynamic +symmetric-point tracking. Their correction acts on how a requested gradient +update is written into a device. SDIL acts on the measured local teaching +signal that generates the requested update. Its implementation uses the same +edge's task and instruction-off measurements, so it also applies when the +teaching rule itself is contrastive and local. + ## Main figures 1. Method and transfer across Dual Propagation, EP, standard CLLN, and |