From 694ef40bb4dc7e16dbfcefec233055c4de396e80 Mon Sep 17 00:00:00 2001 From: YurenHao0426 Date: Sat, 29 Aug 2026 16:34:19 -0500 Subject: fix: separate autozero SPICE switching phases --- experiments/spice_autozero_primitive_p8.py | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'experiments') diff --git a/experiments/spice_autozero_primitive_p8.py b/experiments/spice_autozero_primitive_p8.py index 9955543..3dec783 100644 --- a/experiments/spice_autozero_primitive_p8.py +++ b/experiments/spice_autozero_primitive_p8.py @@ -29,13 +29,15 @@ def netlist( leakage_resistance_ohm: float, ) -> str: switch_time = acquisition_seconds - transition_time = switch_time + 1.0e-9 - measurement_start = transition_time + 5.0e-9 - measurement_end = transition_time + LEARNING_WINDOW_SECONDS + switch_transition_end = switch_time + 1.0e-9 + raw_transition_start = switch_time + 10.0e-9 + raw_transition_end = switch_time + 11.0e-9 + measurement_start = switch_time + 20.0e-9 + measurement_end = measurement_start + LEARNING_WINDOW_SECONDS simulation_end = measurement_end + 1.0e-6 return f"""Hardware auto-zero primitive sanity check -Vraw raw 0 PWL(0 {OFFSET_V} {switch_time} {OFFSET_V} {transition_time} {OFFSET_V + LEARNING_SIGNAL_V} {simulation_end} {OFFSET_V + LEARNING_SIGNAL_V}) -Vsample sample 0 PWL(0 5 {switch_time} 5 {transition_time} 0 {simulation_end} 0) +Vraw raw 0 PWL(0 {OFFSET_V} {raw_transition_start} {OFFSET_V} {raw_transition_end} {OFFSET_V + LEARNING_SIGNAL_V} {simulation_end} {OFFSET_V + LEARNING_SIGNAL_V}) +Vsample sample 0 PWL(0 5 {switch_time} 5 {switch_transition_end} 0 {simulation_end} 0) Ssample raw hold sample 0 sample_switch .model sample_switch SW(Ron={switch_resistance_ohm} Roff=1e12 Vt=2.5 Vh=0.1) Chold hold 0 {hold_capacitance_f} IC=0 -- cgit v1.2.3