# Three-part paper evidence

## One-sentence claim

Somato-dendritic innovation is a local correction for predictable teaching-
channel error. It transfers across digital local learners, preserves coupled
learning as the number of imperfect components grows, and can be implemented
with local sampling and subtraction in a hardware-realistic Contrastive Local
Learning Network (CLLN).

The method remains:

```text
r = a - P(z)
Delta w = eta * r * eligibility
```

`P` is fitted from instruction-off local observations. It receives no task
gradient, device constant, downstream weight, or BP signal.

## Part 1: additive digital correction

The first part asks whether the same operation can be attached to an existing
learning rule without replacing that rule.

| Digital learner | Task and repetitions | Clean | Raw imperfection | Static calibration | SDIL | Status |
|:--|:--|--:|--:|--:|--:|:--|
| Dual Propagation | CIFAR-10 miniCNN, 5 seeds | 82.86% | 9.40% | — | 82.92% | Passed frozen confirmation |
| Equilibrium Propagation | FashionMNIST ConvHopfield, 5 seeds | 76.26% | 31.38% | 67.90% | 74.52% | SDIL beats raw in every seed; strict gate failed because one seed favors calibration |
| Digital coupled learning | 32-edge ring tasks, 40 tasks × 3 draws | 100.00% | 65.31% | 93.85% | 100.00% | Passed frozen confirmation |
| Overclamped coupled learning | 32-edge ring tasks, 40 tasks × 3 draws | 91.88% | 66.88% | — | 91.98% | Passed frozen confirmation |

Sources:

- `results/contrastive_bias/c1_gate.json`
- `results/ep_bias/c1_gate.json`
- `results/coupled_ladder/p2_confirm_side4.json`
- `results/coupled_ladder/p3_overclamp_side4.json`

The Dual Propagation result establishes strong transfer. The EP result shows
transfer with a visible remaining clean gap and seed variance. Coupled learning
adds a system where the local variables map directly to circuit measurements.

## Part 2: scaling digital coupled learning

The periodic grid ladder uses side lengths `4, 8, 12, 16, 24, 32`, or 32 to
2,048 learnable edges. Every method receives the same released task, tiled
initial gate field, and component draw. Size-dependent update exposure is
selected from ideal coupled learning only.

The circuit equations, released 4-by-4 task panel, and component-error scales
come from [Dillavou et al. (2025)](https://arxiv.org/abs/2505.22887). Larger
periodic grids preserve the same local device law and learning primitive.

Confirmed final classification error:

| Edges | Clean | Same-RMS noise | Raw | Static calibration | SDIL |
|--:|--:|--:|--:|--:|--:|
| 32 | 0.00% | 0.73% | 34.69% | 6.15% | 0.00% |
| 128 | 1.25% | 2.60% | 37.92% | 6.46% | 1.25% |
| 288 | 1.88% | 8.02% | 48.12% | 6.35% | 1.88% |
| 512 | 2.50% | 11.35% | 47.71% | 9.58% | 2.50% |
| 1,152 | 2.50% | 19.38% | 48.44% | 18.13% | 2.92% |
| 2,048 | 1.56% | 26.67% | 49.90% | 27.19% | 2.29% |

The raw learner has a large error floor at every size. Same-RMS noise and
static calibration both degrade as the grid grows. Relative to static
calibration, SDIL reduces the excess final-error growth slope by 96.2% (paired
task-bootstrap 95% interval 93.0% to 98.5%) and the excess stable-failure
growth slope by 89.5% (74.8% to 96.6%). Its excess error-AUC slope is slightly
negative, eliminating the corresponding positive static-calibration slope.
At 2,048 edges, SDIL closes 98.5% of the raw-to-clean final-error gap and
reaches stable zero error on 82.5% of trials, versus 0% for raw, 23.3% for
static calibration, and 87.5% for clean.

The improvement has a measurement cost. At 2,048 edges SDIL uses 3,487 local
updates to the censored stable-zero target on average, versus 4,548 for static
calibration. Counting task and neutral edge measurements, SDIL uses 14.28
million local scalar reads versus 9.35 million for static calibration, a
1.53-times ratio. Runs that miss stable zero receive the frozen 600-epoch
horizon in both cost summaries.

A frozen sampling-budget control increases static calibration from 16 to 256
instruction-off observations per edge at 2,048 edges. Final error changes from
27.19% to 30.31%; the paired improvement is -3.13 percentage points with a
95% interval from -5.94 to -0.31. Stable-zero fraction changes from 23.33% to
20.00%. The preregistered decision is `sampling_limited=false`.

The overclamp confirmation is complete through 1,152 edges. At that size,
clean overclamping, imperfect overclamping, and overclamping plus SDIL end at
1.25%, 45.31%, and 1.25% error. The 2,048-edge endpoint is still running.

The publication figure and data are:

- `results/figs/figure_clln_scaling_confirmation.pdf`
- `results/figs/figure_clln_scaling_confirmation_resources.pdf`
- `results/coupled_ladder/p2_scaling_analysis.json`
- `results/coupled_ladder/p2_scaling_source.csv`

The mechanism statement is now explicit in `THEORY.md`. For a local
state-dependent component error, conditional subtraction removes at least as
much mean-square bias as a constant calibration. Residual component power adds
with edge count. In a local quadratic objective, persistent residual bias
produces an exact displaced optimum with excess objective
`0.5 * delta^T H^+ delta`; the classification ladder tests whether this local
effect reaches the downstream task endpoint.

The confirmation contains all 40 released tasks, three new component draws,
six sizes, and five core methods: 3,600 completed training trajectories. Its
outputs are
`results/coupled_ladder/p2_confirm_side{4,8,12,16,24,32}.json`.

## Part 3: hardware-realistic simulation

This part uses the nonlinear conductance law, periodic 4-by-4 topology,
released Figure-5 tasks and initial gates, Appendix-C component imperfections,
and explicit local voltage-square updates.

A descriptive reanalysis of released physical drift traces first checks the
problem assumption. Per-edge local affine bias reduces held-out RMSE to 0.21
and 0.54 of a constant-bias model in the two released task pairs. This shows a
measured state-dependent component; it does not show SDIL training on
fabricated hardware.

The untouched confirmation uses 40 tasks and three new component draws, or 120
trials per method:

| Method | Mean classification error | Zero-error trials |
|:--|--:|--:|
| Clean CLLN | 0.00% | 100.00% |
| Raw imperfect CLLN | 25.42% | 18.33% |
| Static calibration | 1.35% | 92.50% |
| Clean overclamping | 0.00% | 100.00% |
| Imperfect overclamping | 5.42% | 85.83% |
| SDIL | 0.00% | 100.00% |
| Overclamping + SDIL | 0.00% | 100.00% |

The local CDS/autozero circuit model then adds sampling gain mismatch,
pedestal mismatch, noise, and stale refresh. Ideal CDS and the combined mild
refresh-every-four condition retain 0% error. The combined strong condition
has 0.55% mean error and 96.88% zero-error trials. A 0.1 V/s pedestal mismatch
has 0.63% error; a 0.25 V/s mismatch has 4.45% error and marks the simulated
failure boundary.

Sources:

- `results/physical_bias/p11_nonlinear_hardware_confirmation.json`
- `results/physical_bias/p11_nonlinear_hardware_confirmation_gate.json`
- `sdil/physical_grid.py`
- `results/physical_bias/p5_full_grid_bias_crossover.json`
- `results/physical_bias/p9_grid_correlated_autozero_key_results.json`
- `results/physical_bias/p8_spice_autozero_primitive.json`
- `results/figs/figure_physical_hardware_evidence_confirmation.pdf`
- `results/physical_bias/p12_hardware_evidence_analysis.json`
- `results/physical_bias/p0_state_dependence.json`
- `results/figs/physical_bias_state_dependence.png`

The hardware claim is: the full update is simulated with published device
equations and nonideal local sampling, and its primitive sample/subtract path
has a SPICE check. A fabricated-chip demonstration remains future work.

## Closest hardware-correction methods

[Dillavou et al. (2025)](https://arxiv.org/abs/2505.22887) identify biased
local updates in a physical CLLN and introduce overclamping. Their appendix
describes each edge's actual bias as an unknown deterministic function of
system state, while their tractable dynamics use a fixed bias vector. This is
the direct experimental problem behind the state-dependent ladder.

[Wu et al. (2025)](https://arxiv.org/abs/2502.06309) and
[Xiao et al. (2026)](https://arxiv.org/abs/2602.21321) correct asymmetric
conductance updates in analog in-memory SGD using residual arrays or dynamic
symmetric-point tracking. Their correction acts on how a requested gradient
update is written into a device. SDIL acts on the measured local teaching
signal that generates the requested update. Its implementation uses the same
edge's task and instruction-off measurements, so it also applies when the
teaching rule itself is contrastive and local.

## Main figures

1. Method and transfer across Dual Propagation, EP, standard CLLN, and
   overclamped CLLN.
2. Digital CLLN scaling: final error, stable success, and learning curves.
3. Hardware-realistic CLLN: raw, calibration, overclamping, SDIL, and
   nonideal-CDS robustness.
4. Mechanism boundary: matched noise, state dependence, sampling mismatch,
   and refresh interval.

## Remaining gates

1. Finish the 2,048-edge overclamp endpoint and rebuild its scaling figure.
2. Audit every manuscript number against its source JSON.