Intercept: Shanbhag draft A superseded — die modes answered NO on published record, ask inverted

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_014FAPDWQ49M5Ye3NpTndTpn

1 files changed, 13 insertions, 1 deletions

diff --git a/docs/outreach/OUTREACH_TARGETS.md b/docs/outreach/OUTREACH_TARGETS.md
index 28934ef..0d1b621 100644
--- a/docs/outreach/OUTREACH_TARGETS.md
+++ b/docs/outreach/OUTREACH_TARGETS.md
@@ -68,7 +68,19 @@ plan are attached.
 
 Best, Yuren
 
-### Draft A (wave-1b) — Shanbhag group · To: Soonha Hwang (soonhah2@), Mihir Kavishwar (mihirvk2@) · cc: Shanbhag
+### ⛔ Draft A SUPERSEDED 2026-07-13 — DO NOT SEND AS-IS (M-scale down-select §6)
+The published record answers the die-mode questions NO: the 65nm DIMA trainer's outputs are 3
+comparators + a 6b test-ADC pair (JSSC-2018, author PDF), and the 28nm ESSERC chip is a **Digital
+IMC** by the group's own Nov-2025 slides. Pitching "your CIM as our EP substrate" would show we
+hadn't read their papers. The INVERTED ask (amended wording from the audit, use verbatim or close):
+"We've read the JSSC-2018 die docs — the 512x256 bank's outputs are comparator decisions plus the
+6b test ADC pair, and the 28nm DiT is digital IMC per your Nov-2025 deck. Two questions: does ANY
+die variant in the group's inventory expose per-column analog outputs before aggregation, and would
+you co-design a per-column two-phase contrast-readout macro on a future run?" Plus: harness/gateware
+collaboration + digital-IMC baseline are their real near-term value; the T64 gateware ports
+unchanged to any future analog macro. Rewrite Draft A around this before sending.
+
+### Draft A (wave-1b, STALE — see banner above) — Shanbhag group · To: Soonha Hwang (soonhah2@), Mihir Kavishwar (mihirvk2@) · cc: Shanbhag
 Subject: Backprop-free transformer training — GPU-scale results and a staged path to CIM
 
 Hi Soonha and Mihir,