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| author | Yuren Hao <yurenh2@illinois.edu> | 2026-07-15 10:32:26 -0500 |
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| committer | Yuren Hao <yurenh2@illinois.edu> | 2026-07-15 10:32:26 -0500 |
| commit | a6d88a18a4bfd46ab0dd487730b72dcbc3b8b5b8 (patch) | |
| tree | ad6a724c445958c8e5ddca1906fdd9bc63a764a2 /assets/hw | |
| parent | 82da86dbd49a093a24e0827331667e8e9e6217df (diff) | |
assets/: organize into decks|figs|hw|refs|misc; scripts + gitignore repointed
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_014FAPDWQ49M5Ye3NpTndTpn
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| -rw-r--r-- | assets/hw/CLOCKLESS_ANALOG_MVP_PLAN.html | 509 | ||||
| -rw-r--r-- | assets/hw/COLLABORATOR_BRIEF.html | 98 | ||||
| -rw-r--r-- | assets/hw/hw_mvp_explainer.html | 220 | ||||
| -rw-r--r-- | assets/hw/hw_outreach_pack.zip | bin | 0 -> 188976 bytes |
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diff --git a/assets/hw/CLOCKLESS_ANALOG_MVP_PLAN.html b/assets/hw/CLOCKLESS_ANALOG_MVP_PLAN.html new file mode 100644 index 0000000..a2e1e07 --- /dev/null +++ b/assets/hw/CLOCKLESS_ANALOG_MVP_PLAN.html @@ -0,0 +1,509 @@ +<!DOCTYPE html><html><head><meta charset='utf-8'><style> +body { font-family: 'Helvetica Neue', Arial, sans-serif; font-size: 10.5pt; line-height: 1.38; + max-width: 46em; margin: 0 auto; color: #111; } +h1 { font-size: 15pt; border-bottom: 2px solid #333; padding-bottom: 4px; margin-top: 0.4em;} +h2 { font-size: 12pt; margin-top: 1.1em; border-bottom: 1px solid #bbb; padding-bottom: 2px; } +h3 { font-size: 11pt; margin-top: 1em; } +table { border-collapse: collapse; margin: 0.6em 0; font-size: 9.5pt; } +th, td { border: 1px solid #999; padding: 3px 7px; text-align: left; } +th { background: #eee; } +code, pre { font-family: Menlo, Consolas, monospace; font-size: 9pt; background: #f4f4f4; } +pre { padding: 7px 10px; border: 1px solid #ddd; overflow-x: hidden; white-space: pre-wrap; } +blockquote { border-left: 3px solid #888; margin-left: 0; padding-left: 12px; color: #333; } +li { margin: 2px 0; } +@page { margin: 16mm 15mm; } +</style></head><body><h1>Clockless analogue MVP for physical EP research</h1> +<p><strong>Prepared:</strong> 2026-07-11<br /> +<strong>Starting point:</strong> <code>COMPONENT_HW_MAP.md</code><br /> +<strong>Scope:</strong> academic prototype, not a product demonstrator; analogue learning core; no processor, ADC, DAC, FPGA, sample-and-hold bank, phase clock, or digital optimizer in the learning loop.</p> +<hr /> +<h2>1. Executive decision</h2> +<p>The current <code>$5k–$20k</code> Demo-0 is not an MVP. It is an architecture demonstrator that tries to validate, at once, an SRAM-CIM module, bidirectional transpose reads, RoPE mixers, QK/RMS normalization, analogue softmax, SwiGLU multipliers, analogue state handling, ADC/DAC boundaries, a phase sequencer, write programming, and digital supervisory logic. A failure would be difficult to attribute to one mechanism.</p> +<p>The lower-risk research question is narrower and more publishable:</p> +<blockquote> +<p>Can a reciprocal nonlinear analogue network continuously learn by a local equilibrium contrast, with the free and nudged states physically present at the same time, without a clock or processor in the learning loop?</p> +</blockquote> +<p>Build that first. The recommended core is a <strong>twin-equilibrium analogue learning tile</strong>:</p> +<ul> +<li>two small physical replicas of the same reciprocal nonlinear resistor network;</li> +<li>corresponding trainable edges share one analogue weight capacitor;</li> +<li>both replicas run continuously, so there are no sequential free/nudged phases;</li> +<li>an output OTA supplies a true EP-style current nudge; a jumper also provides a voltage-clamped Coupled Learning control condition;</li> +<li>each edge updates its own capacitor from a local contrast;</li> +<li>manual boundary-condition selection and a manual learn/freeze switch replace an FPGA;</li> +<li>a scope or DMM may observe the circuit but is not part of the feedback or learning path.</li> +</ul> +<p>Recommended first populated board: <strong>8 sign-update edges plus one exact multiplier reference channel</strong>, approximately <strong>$170–$300</strong> excluding instruments, tax, and shipping. This is about <strong>17×–118× below</strong> the current <code>$5k–$20k</code> board class. A one-edge calibration rig is approximately <strong>$70–$130</strong>.</p> +<hr /> +<h2>2. What “completely analogue and clockless” can honestly mean</h2> +<p>A defensible claim is:</p> +<blockquote> +<p>The state evolution, nudge, local learning rule, and weight storage are continuous-time analogue processes. No periodic control signal, processor, converter, sampled state memory, or digitally computed parameter update participates in learning.</p> +</blockquote> +<p>Allowed outside the claim:</p> +<ul> +<li>a bench supply;</li> +<li>an oscilloscope or DMM used only for observation;</li> +<li>a human changing input/target switches;</li> +<li>a static mechanical learn/freeze switch;</li> +<li>offline analysis after an experiment.</li> +</ul> +<p>A full language-model demonstration cannot honestly be entirely analogue and clockless at the token interface: symbol lookup, presentation of a sequence, cross-entropy labels, and token sampling are discrete operations. The academic MVP should therefore validate the <strong>physical learning primitive</strong>, then add a very small reciprocal attention cell as a second experiment.</p> +<hr /> +<h2>3. Core topology</h2> +<pre><code class="language-text"> analogue input x analogue target y* + │ │ + ┌────────────┴────────────┐ │ + │ │ │ + ▼ ▼ │ + FREE reciprocal network NUDGED reciprocal network + natural RC settling natural RC settling + output y0 output yβ + nudge current + │ ▲ │ + │ │ OTA/error transconductor + │ └──────────────┘ + │ + for every trainable edge e: + + edge voltage Δv0,e edge voltage Δvβ,e + │ │ + └──── local contrast cell ─────┘ + │ + charge/discharge current + │ + shared weight Cw,e + │ + ┌────────────┴────────────┐ + ▼ ▼ + MOSFET edge in free net MOSFET edge in nudged net +</code></pre> +<p>The two replicas must be laid out symmetrically and use matched transistor pairs where practical. The shared capacitor ensures both edge copies always use the same learned weight.</p> +<h3>3.1 State dynamics</h3> +<p>The node voltages are the states. Resistors/MOSFET conductances and node capacitances produce the relaxation automatically. Add small capacitors only where needed to set a reproducible pole and suppress oscillation; do not build a capacitor-plus-OTA integrator for every abstract model state.</p> +<p>Design target, not a theorem:</p> +<pre><code>τ_{weight}/τ_state ≥ 10^2, preferably 10^3. +</code></pre> +<p>The state should equilibrate much faster than the weight capacitors move. This time-scale separation replaces a settle detector and phase sequencer.</p> +<h3>3.2 True EP nudge and the CL control</h3> +<p>Populate both modes on the same board.</p> +<p><strong>EP mode — current/force nudge.</strong> For voltage outputs, compute the output error and inject a proportional current at the nudged output. A practical small-nudge implementation is</p> +<pre><code>I_β = -g_β (y_0-y^*) +</code></pre> +<p>with an LM13700-class OTA or a discrete transconductor. The polarity is chosen to push the nudged output toward the target. This crosses voltage error with current nudge and is the mode to use for the formal EP/gradient-flow claim.</p> +<p><strong>CL mode — voltage constraint.</strong> Buffer a weighted voltage between the free output and the target and impose it on the second replica. This is easier and reproduces the demonstrated clockless Coupled Learning architecture, but it should not be called exact EP.</p> +<p>A two-position switch should select EP-current or CL-voltage nudge. That comparison is itself a useful experiment.</p> +<h3>3.3 Exact local contrast</h3> +<p>For a conductance-like parameter, the local energy derivative is proportional to the squared voltage drop. Use</p> +<pre><code>C_{w,e} dV/dt_{w,e} + = s_e k≤ft[(\Delta v_{β,e})^2-(\Delta v_{0,e})^2], +</code></pre> +<p>where <code>s_e = ±1</code> accounts for whether increasing capacitor voltage increases or decreases effective conductance.</p> +<p>Do not square twice. Use</p> +<pre><code>a^2-b^2=(a-b)(a+b), +</code></pre> +<p>so one four-quadrant multiplier can implement an exact reference channel. The established laboratory circuit used an AD633 with op-amp conditioning and a local capacitor.</p> +<h3>3.4 Low-cost sign contrast</h3> +<p>The exact multiplier dominates cost. A much cheaper local rule is</p> +<pre><code>C_{w,e} dV/dt_{w,e} + = s_e I_0 sgn≤ft(|\Delta v_{β,e}|-|\Delta v_{0,e}|) +</code></pre> +<p>outside a deadband <code>δ</code>, with zero current inside the deadband. Implement it with absolute-value/rectifier stages, a comparator with hysteresis, and two matched charge/discharge current sources.</p> +<p>This rule has precedent in simulated memristor EP hardware because it removes the analogue multiplier. The <strong>continuous capacitor implementation proposed here is an engineering adaptation</strong>, not an already demonstrated result. That is a legitimate research contribution, but it must be labeled correctly.</p> +<h3>3.5 Freeze and retention</h3> +<p>Use a mechanical toggle or relay to disconnect update current from every weight capacitor. Avoid a clocked switch matrix. Use film capacitors initially; characterize leakage and dielectric absorption. Volatile analogue weights are acceptable for an academic demonstrator, but not for a storage product.</p> +<hr /> +<h2>4. Recommended hardware ladder</h2> +<h3>Rung A — one-edge metrology tile</h3> +<p>Purpose: validate the physics before assembling a network.</p> +<p>Populate:</p> +<ul> +<li>one free/nudged MOSFET pair;</li> +<li>one shared weight capacitor;</li> +<li>one exact AD633 contrast path;</li> +<li>one sign-only contrast path selectable by jumper;</li> +<li>one EP-current nudge OTA;</li> +<li>one CL-voltage nudge path;</li> +<li>test points for all four edge terminals, multiplier inputs/output, capacitor current, and weight voltage.</li> +</ul> +<p>Estimated cost: <strong>$70–$130</strong>.</p> +<p>Required measurements:</p> +<ol> +<li>transfer surface <code>I_update(Δv0, Δvβ)</code>;</li> +<li>exact-channel gain and offset;</li> +<li>sign-channel boundary, hysteresis, and deadband;</li> +<li>zero-contrast drift at <code>Δv0 = Δvβ</code>;</li> +<li>weight retention with learning frozen;</li> +<li>temperature drift;</li> +<li>nudge linearity versus <code>β</code>;</li> +<li>time-scale ratio between node settling and weight motion.</li> +</ol> +<p>Do not build the multi-edge board until this tile gives a stable null at zero contrast.</p> +<h3>Rung B — two modular four-edge cards</h3> +<p>Build a four-edge card and populate two cards for eight trainable edges. Each card contains:</p> +<ul> +<li>four twin MOSFET edges;</li> +<li>four sign-update cells;</li> +<li>four weight capacitors;</li> +<li>local trim/deadband points;</li> +<li>a shared learn/freeze bus that is static, not clocked;</li> +<li>edge terminals on headers so the network topology is patchable.</li> +</ul> +<p>Recommended population: eight sign channels plus <strong>one parallel exact AD633 channel on a selected edge</strong>. This gives a continuously measured exact-versus-sign comparison without buying eight multipliers.</p> +<p>Estimated cost: <strong>$170–$300</strong>.</p> +<p>Initial task:</p> +<ul> +<li>one-input nonlinear regression with 4–8 manually selected static examples;</li> +<li>then a two-input task after topology simulation and one-edge characterization.</li> +</ul> +<p>Do not promise XOR at eight edges. The published nonlinear clockless network used 32 twin edges for XOR. Design the card so eight identical four-edge modules can be stacked later.</p> +<h3>Rung C — 32-edge replication-class network</h3> +<p>Use eight four-edge cards and the sign-update rule. This approaches the scale of the published nonlinear demonstration while avoiding 32 AD633 multipliers.</p> +<p>Estimated cost: <strong>$450–$900</strong>.</p> +<p>This is still below the low end of the original plan by approximately <strong>5.5×–44×</strong> and is large enough for a serious robustness and nonlinear-learning study.</p> +<h3>Rung D — reciprocal attention microcell</h3> +<p>Only after Rungs A–C work, add a transformer-adjacent cell:</p> +<ul> +<li>two tokens;</li> +<li>one head;</li> +<li>scalar or two-dimensional state;</li> +<li>tied key/value or another explicitly energy-based reciprocal construction;</li> +<li>hardwired causal connectivity;</li> +<li>no embedding memory, RoPE, RMSNorm, QK norm, SwiGLU, ADC, LM head, or token sampler.</li> +</ul> +<p>For two alternatives, softmax reduces to a logistic function of a score difference, so a differential pair can replace a general <code>N</code>-way entropic-resistor array. This is an <strong>attention-shaped energy cell</strong>, not an OLMo2 block.</p> +<p>Estimated total including the learning core: <strong>$300–$700</strong>.</p> +<hr /> +<h2>5. Costed options</h2> +<p>Budgetary single-quantity catalogue prices checked on 2026-07-11; prices exclude tax, shipping, instruments, assembly labor, and rework.</p> +<table> +<thead> +<tr> +<th>Item</th> +<th style="text-align: right;">Planning role</th> +<th style="text-align: right;">Unit price used</th> +<th style="text-align: right;">Planning quantity, 8-edge board</th> +<th style="text-align: right;">Extended</th> +</tr> +</thead> +<tbody> +<tr> +<td>ALD1106PBL</td> +<td style="text-align: right;">matched N-MOS array; two twin edges/package</td> +<td style="text-align: right;">$9.29</td> +<td style="text-align: right;">4</td> +<td style="text-align: right;">$37.16</td> +</tr> +<tr> +<td>AD633ANZ</td> +<td style="text-align: right;">exact four-quadrant contrast multiplier</td> +<td style="text-align: right;">$21.48</td> +<td style="text-align: right;">0, 1, or 8</td> +<td style="text-align: right;">$0 / $21.48 / $171.84</td> +</tr> +<tr> +<td>TLV274IPWR</td> +<td style="text-align: right;">quad rail-to-rail op amp</td> +<td style="text-align: right;">$1.43</td> +<td style="text-align: right;">6–8</td> +<td style="text-align: right;">$8.58–$11.44</td> +</tr> +<tr> +<td>LM13700</td> +<td style="text-align: right;">dual OTA; output nudge/current sources</td> +<td style="text-align: right;">$1.70</td> +<td style="text-align: right;">1–2</td> +<td style="text-align: right;">$1.70–$3.40</td> +</tr> +<tr> +<td>LM339-class comparator</td> +<td style="text-align: right;">sign/deadband channels</td> +<td style="text-align: right;">about $0.67</td> +<td style="text-align: right;">2–4</td> +<td style="text-align: right;">about $1.34–$2.68</td> +</tr> +<tr> +<td>CD4066-class switch</td> +<td style="text-align: right;">optional static freeze/routing</td> +<td style="text-align: right;">about $0.73–$0.97</td> +<td style="text-align: right;">2–4</td> +<td style="text-align: right;">about $1.46–$3.88</td> +</tr> +<tr> +<td>Film capacitors</td> +<td style="text-align: right;">weight storage</td> +<td style="text-align: right;">about $0.63 at 1 µF</td> +<td style="text-align: right;">8–12</td> +<td style="text-align: right;">about $5–$8</td> +</tr> +<tr> +<td>Diodes, resistors, trims</td> +<td style="text-align: right;">rectifiers, limits, biasing</td> +<td style="text-align: right;">—</td> +<td style="text-align: right;">lot</td> +<td style="text-align: right;">$15–$40</td> +</tr> +<tr> +<td>PCB/protoboard, headers, test points</td> +<td style="text-align: right;">physical implementation</td> +<td style="text-align: right;">—</td> +<td style="text-align: right;">lot</td> +<td style="text-align: right;">$35–$120</td> +</tr> +<tr> +<td>Power rails, protection, spare parts</td> +<td style="text-align: right;">laboratory overhead</td> +<td style="text-align: right;">—</td> +<td style="text-align: right;">lot</td> +<td style="text-align: right;">$30–$90</td> +</tr> +</tbody> +</table> +<p>Resulting envelopes:</p> +<table> +<thead> +<tr> +<th>Variant</th> +<th style="text-align: right;">Estimated build cost</th> +<th>Recommendation</th> +</tr> +</thead> +<tbody> +<tr> +<td>One-edge exact/sign calibration tile</td> +<td style="text-align: right;">$70–$130</td> +<td>Build first</td> +</tr> +<tr> +<td>8-edge sign-only</td> +<td style="text-align: right;">$140–$250</td> +<td>Cheapest useful network</td> +</tr> +<tr> +<td>8-edge sign + one exact reference channel</td> +<td style="text-align: right;">$170–$300</td> +<td><strong>Recommended MVP</strong></td> +</tr> +<tr> +<td>8-edge all-exact AD633</td> +<td style="text-align: right;">$300–$500</td> +<td>Only after reference channel works</td> +</tr> +<tr> +<td>32-edge sign-update network</td> +<td style="text-align: right;">$450–$900</td> +<td>Replication-class nonlinear demo</td> +</tr> +<tr> +<td>Reciprocal two-token attention add-on</td> +<td style="text-align: right;">+$100–$250</td> +<td>Phase 2 only</td> +</tr> +</tbody> +</table> +<h3>Aggressive transistor substitution</h3> +<p>A CD4007UBE costs about <code>$0.89</code> and contains a CMOS dual complementary pair plus inverter. It can be explored on the one-edge tile, but it is not the main-board recommendation: matching, body connections, and device operating region become the dominant uncertainty. Saving roughly <code>$30</code> of matched-transistor cost on an eight-edge board is not worth sacrificing the experiment’s interpretability.</p> +<hr /> +<h2>6. Delete list for the original plan</h2> +<p>For the academic MVP, delete these entirely:</p> +<ul> +<li>SRAM-CIM, Mythic, HERMES, or other accelerator evaluation board;</li> +<li>FPGA and phase sequencer;</li> +<li>DAC and ADC arrays;</li> +<li>token embedding lookup;</li> +<li>RoPE DDS and mixers;</li> +<li>full causal softmax array;</li> +<li>QK normalization;</li> +<li>RMSNorm banks;</li> +<li>SwiGLU multiplier array;</li> +<li>digital cross-entropy head;</li> +<li>Adam/Muon or any digital optimizer;</li> +<li>crossbar write-programming machinery;</li> +<li>sampled free-phase memories;</li> +<li>digital settle/retry logic;</li> +<li>GPU gradient telemetry.</li> +</ul> +<p>Keep or replace as follows:</p> +<table> +<thead> +<tr> +<th>Original function</th> +<th>MVP replacement</th> +</tr> +</thead> +<tbody> +<tr> +<td>MVM/crossbar</td> +<td>patchable reciprocal nonlinear resistor network</td> +</tr> +<tr> +<td>state integrators</td> +<td>natural RC/KCL state dynamics</td> +</tr> +<tr> +<td>sequential free/nudged phases</td> +<td>two continuously operating physical replicas</td> +</tr> +<tr> +<td>DAC nudge</td> +<td>OTA current injection</td> +</tr> +<tr> +<td>digital phase memory</td> +<td>simultaneous physical state comparison</td> +</tr> +<tr> +<td>outer-product update/programming</td> +<td>local capacitor charge/discharge</td> +</tr> +<tr> +<td>FPGA control</td> +<td>manual boundary selection and learn/freeze</td> +</tr> +<tr> +<td>ADC telemetry</td> +<td>buffered scope/DMM observation outside loop</td> +</tr> +</tbody> +</table> +<hr /> +<h2>7. Experimental matrix</h2> +<p>The cleanest paper is not merely “it learned.” It should isolate the choices that make the clockless implementation possible.</p> +<h3>Factor 1 — nudge type</h3> +<ul> +<li>EP: voltage error, current nudge;</li> +<li>CL: voltage error, voltage constraint.</li> +</ul> +<h3>Factor 2 — local update</h3> +<ul> +<li>exact difference of squares;</li> +<li>sign-only magnitude comparison;</li> +<li>sign-only with deadband/hysteresis.</li> +</ul> +<h3>Factor 3 — device quality</h3> +<ul> +<li>matched ALD1106 edges;</li> +<li>one-edge CD4007 substitution;</li> +<li>deliberate mismatch or trim-offset injection.</li> +</ul> +<h3>Factor 4 — nudge magnitude</h3> +<ul> +<li>small nudge;</li> +<li>moderate/overclamped nudge;</li> +<li>measured bias-versus-SNR curve.</li> +</ul> +<h3>Factor 5 — operating conditions</h3> +<ul> +<li>temperature;</li> +<li>supply variation;</li> +<li>capacitor leakage/hold time;</li> +<li>damaged or disconnected edge;</li> +<li>topology size.</li> +</ul> +<p>Proposed acceptance criteria, to be declared before network training:</p> +<ol> +<li>no periodic control signal in the learning loop;</li> +<li>no processor, ADC, DAC, or stored free-phase sample used for an update;</li> +<li>exact reference channel has a stable zero-contrast null;</li> +<li>sign channel agrees with the exact channel on update direction in at least 95% of the specified operating grid;</li> +<li>frozen weights remain within the chosen tolerance over the measurement interval;</li> +<li>loss decreases consistently across multiple resets, with all failures reported;</li> +<li>EP-current and CL-voltage modes are labeled separately.</li> +</ol> +<hr /> +<h2>8. Six-week execution plan</h2> +<h3>Week 1 — SPICE and one-edge schematic</h3> +<ul> +<li>simulate the MOSFET edge over the intended node/gate voltage range;</li> +<li>choose <code>Cw</code>, update current, and state capacitance for at least 100× time-scale separation;</li> +<li>simulate exact and sign contrast transfer surfaces;</li> +<li>simulate OTA current nudge and output compliance;</li> +<li>add hard rails on weight voltage.</li> +</ul> +<h3>Week 2 — one-edge breadboard</h3> +<ul> +<li>build only the exact path first;</li> +<li>measure offsets and null drift;</li> +<li>add sign path and deadband;</li> +<li>add manual freeze;</li> +<li>decide whether breadboard leakage is tolerable or proceed directly to PCB.</li> +</ul> +<h3>Week 3 — one-edge characterization</h3> +<ul> +<li>automate only measurement if desired; do not put automation in the learning loop;</li> +<li>produce measured update-vector fields;</li> +<li>identify the safe voltage region;</li> +<li>lock component values for the modular card.</li> +</ul> +<h3>Week 4 — first four-edge card</h3> +<ul> +<li>symmetrical placement;</li> +<li>dense test points;</li> +<li>patchable node topology;</li> +<li>one exact reference edge routed in parallel with its sign cell.</li> +</ul> +<h3>Week 5 — eight-edge network</h3> +<ul> +<li>build a topology selected by SPICE;</li> +<li>train one static example, then 4–8 manually selected regression points;</li> +<li>compare exact-reference and sign decisions continuously.</li> +</ul> +<h3>Week 6 — robustness and paper figures</h3> +<ul> +<li>CL versus EP;</li> +<li>exact versus sign;</li> +<li>mismatch and temperature;</li> +<li>retention and drift;</li> +<li>energy/power by function;</li> +<li>scaling estimate to 32 edges and the reciprocal attention cell.</li> +</ul> +<hr /> +<h2>9. Claims this MVP can and cannot support</h2> +<h3>It can support</h3> +<ul> +<li>a continuous-time analogue physical-learning core;</li> +<li>clockless simultaneous free/nudged operation;</li> +<li>local analogue weight storage and updates;</li> +<li>processor-free learning after boundary conditions are applied;</li> +<li>measured exact-versus-sign update behavior;</li> +<li>measured EP-current-versus-CL-voltage behavior;</li> +<li>nonlinear supervised learning in a small reciprocal network;</li> +<li>a credible scaling BOM.</li> +</ul> +<h3>It cannot support</h3> +<ul> +<li>a full analogue OLMo2 block;</li> +<li>ordinary independent-Q/K/V attention on a passive reciprocal network;</li> +<li>end-to-end clockless language modeling;</li> +<li>nonvolatile weights;</li> +<li>a claim that the sign-only capacitor rule is exact EP;</li> +<li>a claim that voltage-clamped Coupled Learning is identical to EP;</li> +<li>production energy/area numbers derived from a breadboard.</li> +</ul> +<p>A passive reciprocal network avoids the adjoint/transposed-Jacobian problem by construction, but it also excludes normal non-reciprocal attention. The transformer connection must therefore use tied, energy-based attention or be deferred to an active-adjoint phase.</p> +<hr /> +<h2>10. Why this is the better academic MVP</h2> +<p>It tests one scientific claim at a time. Every expensive item in the original plan exists to preserve a nearly complete transformer block. That is appropriate after the physical learning primitive is established, not before it.</p> +<p>The proposed sequence produces publishable intermediate results even if the final nonlinear task fails:</p> +<ul> +<li>measured clockless local-gradient circuit;</li> +<li>exact-versus-sign learning rule;</li> +<li>EP-versus-CL physical comparison;</li> +<li>mismatch-induced bias and its suppression;</li> +<li>analogue weight retention and drift;</li> +<li>modular scaling law;</li> +<li>reciprocal attention microcell.</li> +</ul> +<p>The main recommendation is therefore:</p> +<blockquote> +<p>Build the <code>$70–$130</code> one-edge tile, then the <code>$170–$300</code> eight-edge hybrid board. Do not purchase a CIM evaluation module, FPGA, DAC/ADC bank, or softmax hardware for the MVP.</p> +</blockquote> +<hr /> +<h2>11. Primary references used</h2> +<ol> +<li>Sam Dillavou et al., <strong>“Machine Learning Without a Processor: Emergent Learning in a Nonlinear Electronic Metamaterial,”</strong> arXiv:2311.00537v2 / PNAS (2024). Demonstrated a fully analogue, clockless nonlinear twin-resistor network; 32 twin edges; local capacitive learning; XOR and nonlinear regression. Its implemented rule is Coupled Learning.</li> +<li>Sam Dillavou et al., <strong>“Understanding and Embracing Imperfection in Physical Learning Networks,”</strong> arXiv:2505.22887v2 (2026 revision). Characterizes bias, limit cycles, and system-agnostic suppression of analogue learning imperfections.</li> +<li>Joshua A. McGinnis, Xinbo Li, and Yoichiro Mori, <strong>“Coercivity and Local Convergence of Physical Learning in Linear Circuits,”</strong> arXiv:2606.15443 (2026). Distinguishes EP’s force/current nudge from CL’s voltage constraint and analyzes their gradient-flow structure.</li> +<li>Seung-Hyun Oh et al., <strong>“Memristor Crossbar Circuits Implementing Equilibrium Propagation for On-Device Learning,”</strong> <em>Micromachines</em> 14(7):1367 (2023). Proposes simultaneous free/nudged networks and a sign-only fixed-step update to remove analogue multipliers; results are simulation-oriented for memristor programming.</li> +<li>I. M. Elfadel and J. L. Wyatt, <strong>“The ‘Softmax’ Nonlinearity: Derivation Using Statistical Mechanics and Useful Properties as a Multiterminal Analog Circuit Element,”</strong> NeurIPS 1993. Establishes reciprocal/passive circuit properties of an entropic softmax element.</li> +<li><strong>“How to Train Your Resistive Network: Generalized Equilibrium Propagation and Analytical Learning,”</strong> arXiv:2602.03546 (2026). Gives a single-network projector-based route for linear resistive networks; useful as a future replica-reduction direction, not the first nonlinear build.</li> +</ol></body></html>
\ No newline at end of file diff --git a/assets/hw/COLLABORATOR_BRIEF.html b/assets/hw/COLLABORATOR_BRIEF.html new file mode 100644 index 0000000..48df78c --- /dev/null +++ b/assets/hw/COLLABORATOR_BRIEF.html @@ -0,0 +1,98 @@ +<!DOCTYPE html><html><head><meta charset='utf-8'><style> +body { font-family: 'Helvetica Neue', Arial, sans-serif; font-size: 10.5pt; line-height: 1.38; + max-width: 46em; margin: 0 auto; color: #111; } +h1 { font-size: 15pt; border-bottom: 2px solid #333; padding-bottom: 4px; margin-top: 0.4em;} +h2 { font-size: 12pt; margin-top: 1.1em; border-bottom: 1px solid #bbb; padding-bottom: 2px; } +h3 { font-size: 11pt; margin-top: 1em; } +table { border-collapse: collapse; margin: 0.6em 0; font-size: 9.5pt; } +th, td { border: 1px solid #999; padding: 3px 7px; text-align: left; } +th { background: #eee; } +code, pre { font-family: Menlo, Consolas, monospace; font-size: 9pt; background: #f4f4f4; } +pre { padding: 7px 10px; border: 1px solid #ddd; overflow-x: hidden; white-space: pre-wrap; } +blockquote { border-left: 3px solid #888; margin-left: 0; padding-left: 12px; color: #333; } +li { margin: 2px 0; } +@page { margin: 16mm 15mm; } +</style></head><body><h1>Backprop-free training of transformers — results and a staged hardware program</h1> +<p><strong>One-page brief for hardware-side collaborators · rev. 2026-07-12 · Yuren Hao (UIUC)</strong></p> +<h2>The idea in three sentences</h2> +<p>We train <strong>standard multi-layer transformers</strong> with <strong>Equilibrium Propagation</strong> on a layered energy: +training consists of two relaxation phases and a <strong>local</strong> contrast update per weight — no +backpropagation anywhere — and inference is an ordinary forward pass. On GPU this now works at +language-model scale with essentially no quality gap to backprop. The hardware program starts with +the cheapest object that can validate the physical learning rule — a <strong>clockless twin-network +analog tile (~$300)</strong> — and climbs rung by rung to an in-memory-compute transformer block.</p> +<h2>GPU-scale results (2026-07, measured)</h2> +<ul> +<li><strong>A 12-layer, 42.7M-parameter transformer LM trained for a full epoch (59k steps, 361M tokens) + with no backpropagation in the training loop; it generates coherent text.</strong> To our knowledge the + first transformer language model trained fully this way.</li> +<li><strong>Gap to a tuned, same-architecture backprop control: 0.05 nats</strong> (at 4k steps: statistically + indistinguishable, 3 seeds/arm). Prior backprop-free attempts at scale all report qualitative gaps.</li> +<li>EP step = <strong>3.2× backprop FLOPs</strong> (measured); mixed-precision training validated; the two known + EP-specific instabilities are mechanistically diagnosed and closed (an estimator-SNR floor with a + β-schedule law; a relaxation-contractivity crossing eliminated by norm placement).</li> +<li><strong>Every trained operation chosen analog-implementable:</strong> crossbar MVM, divisive normalization, + fixed I/Q rotations (position code), translinear gated MLP, subthreshold-exponential softmax, + two-phase relaxation for the learning rule.</li> +</ul> +<h2>Measured fault tolerances (fault injection at the trained model)</h2> +<table> +<thead> +<tr> +<th>fault</th> +<th>free</th> +<th>marginal</th> +<th>dead</th> +</tr> +</thead> +<tbody> +<tr> +<td>weight precision</td> +<td><strong>8-bit</strong> (ΔCE +0.004)</td> +<td>6-bit (+0.05)</td> +<td>4-bit</td> +</tr> +<tr> +<td>forward state noise</td> +<td><strong>1%</strong></td> +<td>—</td> +<td>—</td> +</tr> +<tr> +<td>error-channel (nudge) noise</td> +<td><strong>10% relative</strong></td> +<td>30%</td> +<td>—</td> +</tr> +<tr> +<td>divider mismatch / gate gain / phase error</td> +<td>3% / 10% / 0.03 rad</td> +<td>10% / — / 0.1 rad</td> +<td>—</td> +</tr> +</tbody> +</table> +<p>Under every non-fatal fault the learning signal tracks the <em>faulted</em> network (gradient cosine ≈ 0.97 +invariant): <strong>the rule co-adapts to the device.</strong> The only hard spec is ~7-bit effective weights.</p> +<h2>The hardware ladder (each rung publishable alone)</h2> +<ol> +<li><strong>One-edge metrology tile ($70–130):</strong> twin MOSFET edge, shared weight capacitor, exact + (difference-of-squares) and sign-only local update channels, OTA current nudge — no processor, + converter, clock, or sampled memory in the learning loop.</li> +<li><strong>8-edge twin network ($170–300):</strong> nonlinear regression; EP current-nudge vs Coupled-Learning + voltage-clamp on one board; exact-vs-sign update comparison; measured bias-vs-nudge-magnitude + curve (the same β-SNR law we measured in simulation).</li> +<li><strong>32-edge network ($450–900):</strong> replication-class nonlinear tasks, robustness study.</li> +<li><strong>Reciprocal attention microcell (+$100–250):</strong> two tokens, one head, energy-based attention.</li> +<li><strong>CIM transformer block (partner phase):</strong> analog MVM + in-situ two-phase EP weight update — + the piece no shipping analog-AI chip has (all are inference-only or on-chip-backprop).</li> +<li><strong>North star: a few-M-parameter TinyStories LM trained on analog hardware.</strong></li> +</ol> +<h2>What we bring / what we ask</h2> +<p><strong>Bring:</strong> the trained models and recipe, the estimator theory (β-SNR law, stability walls), the +measured tolerance ledger, SPICE-first costed build plan, and parts funding (rungs 1–3 are <$1k). +<strong>Ask (rungs 1–3):</strong> bench access, analog-design mentorship, and/or a student who enjoys discrete +analog — six-week plan, instruments = a scope and a DMM. <strong>Ask (rung 5):</strong> a CIM/mixed-signal +partnership where the substrate expertise is yours and the learning rule is ours.</p> +<p><em>(Detail: CLOCKLESS_ANALOG_MVP_PLAN.md — full BOM, schedule, acceptance criteria, claim limits; +COMPONENT_HW_MAP.md — per-operation analog mapping + tolerance status.)</em></p></body></html>
\ No newline at end of file diff --git a/assets/hw/hw_mvp_explainer.html b/assets/hw/hw_mvp_explainer.html new file mode 100644 index 0000000..4114648 --- /dev/null +++ b/assets/hw/hw_mvp_explainer.html @@ -0,0 +1,220 @@ +<!DOCTYPE html> +<html lang="zh"> +<head> +<meta charset="utf-8"> +<title>无时钟模拟学习板 — 结构图解（给不懂硬件的人）</title> +<style> + body { font-family: -apple-system, "PingFang SC", "Microsoft YaHei", sans-serif; margin: 0; + background: #fafbfd; color: #222; line-height: 1.65; } + .wrap { max-width: 1080px; margin: 0 auto; padding: 28px 20px 80px; } + h1 { color: #13294B; font-size: 26px; border-bottom: 3px solid #E84A27; padding-bottom: 8px; } + h2 { color: #13294B; font-size: 20px; margin-top: 2.2em; } + .lead { font-size: 16.5px; color: #444; } + .lead b { color: #E84A27; } + svg { width: 100%; height: auto; background: white; border: 1px solid #dde3ec; border-radius: 10px; } + .hint { text-align: center; color: #888; font-size: 13px; margin-top: 6px; } + [data-tip] { cursor: help; } + [data-tip]:hover { filter: brightness(1.15) drop-shadow(0 0 4px rgba(232,74,39,.45)); } + #tip { position: fixed; display: none; max-width: 340px; background: #13294B; color: #fff; + padding: 10px 13px; border-radius: 8px; font-size: 13.5px; line-height: 1.5; z-index: 10; + box-shadow: 0 4px 18px rgba(0,0,0,.25); pointer-events: none; } + #tip b { color: #FFB894; } + table { border-collapse: collapse; width: 100%; font-size: 14.5px; } + th, td { border: 1px solid #ccd4e0; padding: 8px 12px; text-align: left; } + th { background: #13294B; color: white; } + tr:nth-child(even) { background: #f0f3f8; } + .steps li { margin: 10px 0; } + .steps b { color: #13294B; } + .chip { display: inline-block; background: #eef1f7; border: 1px solid #ccd4e0; border-radius: 14px; + padding: 3px 12px; margin: 3px 4px; font-size: 13.5px; } + .chip b { color: #E84A27; } + .note { background: #fff7f3; border-left: 4px solid #E84A27; padding: 10px 16px; border-radius: 0 8px 8px 0; + font-size: 14.5px; } +</style> +</head> +<body> +<div class="wrap"> + +<h1>无时钟模拟学习板：它长什么样、为什么能学习</h1> +<p class="lead"> +一句话：这块板子上<b>同时活着两份一模一样的电路</b>——一份自由地"回答问题"（FREE），一份的输出被轻轻拉向正确答案（NUDGED）。 +每个"权重"是一颗电容，它不停地比较自己在两份电路里的受力差异、朝着缩小差异的方向缓慢充放电。 +<b>没有处理器、没有时钟、没有数模转换——物理本身在做训练。</b> +把鼠标悬停在图里任何东西上看它是什么。 +</p> + +<svg viewBox="0 0 1200 620" xmlns="http://www.w3.org/2000/svg"> + <defs> + <marker id="arr" markerWidth="9" markerHeight="9" refX="7" refY="3" orient="auto"> + <path d="M0,0 L7,3 L0,6 Z" fill="#2E8B57"/> + </marker> + </defs> + + <!-- ================== FREE replica ================== --> + <text x="235" y="46" text-anchor="middle" font-size="21" font-weight="bold" fill="#13294B">FREE 网络（自由态）</text> + <text x="235" y="70" text-anchor="middle" font-size="13" fill="#888">自然弛豫，输出 = 网络自己的回答 ŷ</text> + <g data-tip="<b>FREE 网络</b>：真实的物理电路。输入电压加上后，电流按电阻自然流动，节点电压在微秒级"稳定下来"（settle）——这个稳定过程就是 ML 里的前向传播，不需要任何计算指令。"> + <rect x="60" y="85" width="350" height="420" rx="14" fill="#f4f6fa" stroke="#13294B" stroke-width="2"/> + </g> + <!-- nodes --> + <g data-tip="<b>输入节点</b>：一个电压源把输入 x 设成固定电压（比如 0.3V 代表某个特征值）。两份网络收到完全相同的输入。"> + <circle cx="120" cy="170" r="22" fill="white" stroke="#13294B" stroke-width="2.5"/> + <text x="120" y="176" text-anchor="middle" font-size="15" fill="#13294B" font-style="italic">x₁</text> + <circle cx="120" cy="420" r="22" fill="white" stroke="#13294B" stroke-width="2.5"/> + <text x="120" y="426" text-anchor="middle" font-size="15" fill="#13294B" font-style="italic">x₂</text> + </g> + <g data-tip="<b>隐藏节点</b>：中间节点的电压就是 ML 里的"隐层激活值"。它不被任何人直接设定——是电流平衡自己找到的值。"> + <circle cx="245" cy="295" r="22" fill="white" stroke="#13294B" stroke-width="2.5"/> + <text x="245" y="301" text-anchor="middle" font-size="15" fill="#13294B" font-style="italic">h</text> + </g> + <g data-tip="<b>输出节点 ŷ</b>：FREE 网络稳定后，这里的电压就是网络的预测。用示波器可以读它，但读数不参与任何学习回路。"> + <circle cx="360" cy="295" r="22" fill="white" stroke="#13294B" stroke-width="2.5"/> + <text x="360" y="301" text-anchor="middle" font-size="15" fill="#13294B" font-style="italic">ŷ</text> + </g> + <!-- edges with MOSFET boxes --> + <g data-tip="<b>可调边（一个 MOSFET 晶体管）</b>：连接两个节点的"电阻"，导电能力由旁边绿色电容的电压控制——<b>这就是一个权重</b>。板上每条这样的边配一个孪生兄弟（右边网络里位置相同的边），两兄弟永远共享同一颗权重电容。"> + <line x1="140" y1="182" x2="228" y2="285" stroke="#13294B" stroke-width="2.5"/> + <rect x="168" y="216" width="30" height="18" fill="#dfe7f3" stroke="#13294B" stroke-width="1.5"/> + <line x1="140" y1="408" x2="228" y2="305" stroke="#13294B" stroke-width="2.5"/> + <rect x="168" y="342" width="30" height="18" fill="#dfe7f3" stroke="#13294B" stroke-width="1.5"/> + <line x1="267" y1="295" x2="338" y2="295" stroke="#13294B" stroke-width="2.5"/> + <rect x="287" y="286" width="30" height="18" fill="#dfe7f3" stroke="#13294B" stroke-width="1.5"/> + <line x1="139" y1="152" x2="341" y2="282" stroke="#13294B" stroke-width="2.5"/> + <rect x="225" y="196" width="30" height="18" fill="#dfe7f3" stroke="#13294B" stroke-width="1.5"/> + </g> + + <!-- ================== NUDGED replica ================== --> + <text x="875" y="46" text-anchor="middle" font-size="21" font-weight="bold" fill="#E84A27">NUDGED 网络（微推态）</text> + <text x="875" y="70" text-anchor="middle" font-size="13" fill="#888">同样的电路 + 输出被轻拉向目标 y*</text> + <g data-tip="<b>NUDGED 网络</b>：FREE 的物理复制品（同样的布线、配对的晶体管），唯一区别：输出端多了一个小电流，把它往正确答案方向轻推。整个网络因此微微变形——每条边感受到的电压差都和 FREE 侧略有不同，<b>这个差异里藏着梯度</b>。"> + <rect x="700" y="85" width="350" height="420" rx="14" fill="#fff6f2" stroke="#E84A27" stroke-width="2"/> + </g> + <g> + <circle cx="760" cy="170" r="22" fill="white" stroke="#E84A27" stroke-width="2.5"/> + <text x="760" y="176" text-anchor="middle" font-size="15" fill="#E84A27" font-style="italic">x₁</text> + <circle cx="760" cy="420" r="22" fill="white" stroke="#E84A27" stroke-width="2.5"/> + <text x="760" y="426" text-anchor="middle" font-size="15" fill="#E84A27" font-style="italic">x₂</text> + <circle cx="885" cy="295" r="22" fill="white" stroke="#E84A27" stroke-width="2.5"/> + <text x="885" y="301" text-anchor="middle" font-size="15" fill="#E84A27" font-style="italic">h</text> + </g> + <g data-tip="<b>被推的输出 ŷβ</b>：因为 OTA 的小电流，这里的电压介于"网络自己的回答"和"正确答案"之间——偏向正确答案一点点（推力强度 = β）。"> + <circle cx="1000" cy="295" r="22" fill="white" stroke="#E84A27" stroke-width="3"/> + <text x="1000" y="301" text-anchor="middle" font-size="14" fill="#E84A27" font-style="italic">ŷβ</text> + </g> + <g data-tip="<b>可调边（孪生 MOSFET）</b>：和左边网络位置对应的边共享同一颗权重电容——所以两份网络的"权重"永远相同，差别只来自输出端的推力。"> + <line x1="780" y1="182" x2="868" y2="285" stroke="#E84A27" stroke-width="2.5"/> + <rect x="808" y="216" width="30" height="18" fill="#fde4da" stroke="#E84A27" stroke-width="1.5"/> + <line x1="780" y1="408" x2="868" y2="305" stroke="#E84A27" stroke-width="2.5"/> + <rect x="808" y="342" width="30" height="18" fill="#fde4da" stroke="#E84A27" stroke-width="1.5"/> + <line x1="907" y1="295" x2="978" y2="295" stroke="#E84A27" stroke-width="2.5"/> + <rect x="927" y="286" width="30" height="18" fill="#fde4da" stroke="#E84A27" stroke-width="1.5"/> + <line x1="779" y1="152" x2="981" y2="282" stroke="#E84A27" stroke-width="2.5"/> + <rect x="865" y="196" width="30" height="18" fill="#fde4da" stroke="#E84A27" stroke-width="1.5"/> + </g> + <!-- target + OTA --> + <g data-tip="<b>目标 y*</b>：正确答案，也用一个电压表示。只有 NUDGED 网络"知道"它——通过 OTA 的推力间接感受到。"> + <circle cx="1130" cy="295" r="22" fill="#eaf7ef" stroke="#2E8B57" stroke-width="2.5"/> + <text x="1130" y="301" text-anchor="middle" font-size="15" fill="#2E8B57" font-style="italic">y*</text> + </g> + <g data-tip="<b>OTA（跨导放大器，约 $1.7 一颗）</b>：持续测量"输出与目标的差距"，按差距大小注入一股小电流把输出往目标推。推力系数就是 EP 里的 β。它相当于告诉网络："往这边一点点"——但从不告诉任何一条边该怎么改。"> + <path d="M 1060,272 L 1060,318 L 1096,295 Z" fill="#eaf7ef" stroke="#2E8B57" stroke-width="2"/> + <line x1="1022" y1="295" x2="1058" y2="295" stroke="#2E8B57" stroke-width="2" marker-end="url(#arr)"/> + <text x="1078" y="345" text-anchor="middle" font-size="12.5" fill="#2E8B57">电流微推 (β)</text> + </g> + + <!-- ================== weight caps + contrast cells ================== --> + <text x="555" y="115" text-anchor="middle" font-size="15" font-weight="bold" fill="#2E8B57">共享权重 + 学习单元（每条边一套）</text> + <g data-tip="<b>对比单元 + 权重电容（紫框）</b>：每条边配一套。它同时量到这条边在 FREE 侧的电压差 Δv 和在 NUDGED 侧的电压差 Δvβ，比较两者（精确版算 Δvβ²−Δv²，便宜版只取正负号），把成比例的电流灌进绿色电容。<b>电容电压 = 权重</b>，它同时控制左右两个孪生 MOSFET 的导电性。这就是一次"梯度更新"——纯模拟、纯局部、连续发生。"> + <g id="cells"></g> + </g> + + <!-- learn/freeze switch --> + <g data-tip="<b>学习/冻结开关（机械拨杆）</b>：断开所有电容的充电电流 = 冻结权重（相当于 model.eval()）。故意用机械开关而不是芯片——保住"学习回路里没有任何数字器件"的主张。"> + <rect x="505" y="530" width="100" height="34" rx="8" fill="#eef1f7" stroke="#555" stroke-width="1.5"/> + <text x="555" y="552" text-anchor="middle" font-size="12.5" fill="#333">learn / freeze</text> + </g> + <!-- scope --> + <g data-tip="<b>示波器（只看不摸）</b>：观察节点电压用，不在任何反馈或学习回路里。这是"完全模拟"主张允许的唯一仪器。"> + <rect x="1075" y="500" width="90" height="60" rx="8" fill="white" stroke="#888" stroke-width="1.5"/> + <path d="M 1085,540 q 12,-24 24,0 t 24,0 t 24,0" fill="none" stroke="#2E8B57" stroke-width="2"/> + <text x="1120" y="516" text-anchor="middle" font-size="11" fill="#888">示波器</text> + </g> +</svg> +<p class="hint">悬停任何元素查看解释 · 紫框 = 学习单元（对比 + 电容）· 绿 = 权重/目标相关 · 蓝 = FREE · 橙 = NUDGED</p> + +<h2>ML ↔ 电路 词典</h2> +<table> + <tr><th>机器学习里的</th><th>板子上的</th><th>备注</th></tr> + <tr><td>激活值 z</td><td>节点电压</td><td>没人"计算"它——电流平衡自己找到它</td></tr> + <tr><td>权重 w</td><td>一颗电容的电压（控制 MOSFET 导电性）</td><td>非易失升级版 = FeFET（Zhu 组的方向）</td></tr> + <tr><td>前向传播</td><td>RC 自然弛豫（~微秒）</td><td>免费，且天然并行</td></tr> + <tr><td>损失的输出梯度</td><td>OTA 电流 = g·(ŷ − y*)</td><td>只在输出端，任何学习规则都需要这个</td></tr> + <tr><td>反向传播</td><td><b>不存在</b></td><td>被"双生网络 + 局部对比"替代</td></tr> + <tr><td>每个权重的梯度</td><td>该边两侧压降的平方差 Δvβ² − Δv²</td><td>纯局部量——只需要摸自己这条边</td></tr> + <tr><td>optimizer.step()</td><td>电容充/放电（~毫秒-秒）</td><td>学习率 = 充电电流大小</td></tr> + <tr><td>训练循环 / 时钟</td><td><b>不存在</b></td><td>两态同时物理存在 + 快慢时间尺度分离</td></tr> +</table> + +<h2>一次"学习"是怎么发生的（其实是连续的，这里人为分步）</h2> +<ol class="steps"> + <li><b>摆题：</b>手动开关把输入 x 设到两份网络上，把目标 y* 设到 OTA 上。</li> + <li><b>瞬间稳定（微秒级）：</b>两份网络各自弛豫。FREE 的输出是网络自己的回答；NUDGED 的输出被 OTA 拉向正确答案一点点。</li> + <li><b>形变传播：</b>输出端被拉动后，NUDGED 网络<b>全身</b>的电压分布都微微变形——离输出越远变形越小，但每条边都感受得到。这就是"credit assignment 由物理完成"。</li> + <li><b>逐边对比（连续进行）：</b>每条边的学习单元比较自己在两侧的压降，差异越大充电越快。方向恰好是能量下降的方向——数学上等价于梯度下降。</li> + <li><b>慢速累积（毫秒-秒级）：</b>权重电容比节点慢 100–1000 倍，所以在权重看来网络永远是"稳定的"——<b>这个时间尺度差就是时钟的替代品</b>。</li> + <li><b>换题：</b>手动换下一组输入/目标。重复。loss 就这样降下去（Penn 的 32 边版本已经在物理上学会了 XOR 和非线性回归）。</li> +</ol> + +<h2>造价阶梯</h2> +<p> +<span class="chip">① 单边标定件 <b>$70–130</b>（先证明物理）</span> +<span class="chip">② 8 边网络 <b>$170–300</b> ← 推荐 MVP</span> +<span class="chip">③ 32 边 <b>$450–900</b>（复现 Penn 规模）</span> +<span class="chip">④ 注意力微单元 <b>+$100–250</b></span> +<span class="chip">⑤ CIM transformer block（合作方阶段）</span> +</p> + +<div class="note"> +<b>诚实边界</b>（也是给合作者的说法）：这块板子验证的是<b>物理学习原语</b>——无时钟双生 EP、局部模拟更新、真电流 nudge vs 电压钳制的对比—— +<b>不是</b> transformer 本身。它和我们 GPU 侧共享同一条定律：nudge 幅度 vs 噪声的信噪比曲线（我们在 fp32 里测过的 β 定律，这块板会在物理里再测一遍）。 +</div> + +</div> +<div id="tip"></div> +<script> +// draw 4 contrast-cell/cap pairs + dashed pairing lines +const svg = document.querySelector('svg'); +const cells = document.getElementById('cells'); +const pairs = [ + {y: 205, fL: [183, 225], fR: [808, 225]}, + {y: 285, fL: [240, 205], fR: [880, 205]}, + {y: 365, fL: [302, 295], fR: [942, 295]}, + {y: 445, fL: [183, 351], fR: [808, 351]}, +]; +let inner = ''; +pairs.forEach((p, i) => { + inner += ` + <rect x="480" y="${p.y-32}" width="150" height="64" rx="10" fill="#faf7ff" stroke="#7B4FB6" stroke-width="2"/> + <text x="555" y="${p.y-12}" text-anchor="middle" font-size="11.5" fill="#7B4FB6">对比: Δv²β − Δv²</text> + <line x1="543" y1="${p.y+2}" x2="543" y2="${p.y+20}" stroke="#2E8B57" stroke-width="2"/> + <line x1="537" y1="${p.y+6}" x2="549" y2="${p.y+6}" stroke="#2E8B57" stroke-width="3"/> + <line x1="537" y1="${p.y+13}" x2="549" y2="${p.y+13}" stroke="#2E8B57" stroke-width="3"/> + <text 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