HW dossier: OLMo2-standard block analog audit (net win; no new non-reciprocity; 3 new E-tier tolerance items)

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@@ -301,3 +301,37 @@ strictly reduces every hardware demand:
 
 Net: cascade turned depth from the cost driver into a memory line-item, and reduced the demo's
 critical-path collaboration from three groups to one.
+
+## OLMo2-standard block: analog audit (2026-07-10)
+Verdict: **net MORE analog-friendly than the 2019 GPT block** — OLMo2's digital-stability changes
+align 1:1 with analog dynamic-range needs. Per component:
+- **RMSNorm (vs LN): net win.** Pure divisive normalization (square-law + KCL sum + divider), NO
+  mean-subtraction path; reuses the softmax KCL-normalization periphery class. Jacobian
+  (g/r)(I - xx^T/r^2) is SYMMETRIC -> no new PAR/adjoint burden.
+- **Norm-after-sublayer (reordered): net win.** Every injection into the residual current-summing bus
+  is bounded at the branch exit — exactly what a physical summing line wants (pre-norm leaves branch
+  outputs unbounded).
+- **Full-width QK-norm: win.** One square-sum bus per q/k (cheaper periphery than per-head), bounds
+  the analog-softmax exp device input (Elfadel-Wyatt range), symmetric Jacobian.
+- **RoPE (vs learned pos-emb): the biggest win.** Fixed per-position 2x2 rotations = I/Q quadrature
+  mixing — a century-old mixed-signal standard block (cos/sin DDS + multiplying DACs). REMOVES a
+  trainable TxC analog memory (write cycles + drift surface). Feedback path J^T = rotation by -theta
+  = same mixer reused. Orthogonal Jacobian (condition 1).
+- **SwiGLU: neutral.** Gate = elementwise Gilbert/translinear multiply (textbook cell, reuse-doctrine
+  compliant); GELU was already x*Phi(x) = same squasher+multiplier class. 3 narrower MVMs, crossbar
+  area param-matched.
+- **No biases: win.** Every bias was a programmable, trainable, drifting current source/DAC. All gone.
+- **Untied head + final RMSNorm: neutral/win.** LM head + CE live digital-side anyway (no 50k-vocab
+  analog softmax); final RMSNorm bounds the signal crossing the ADC boundary.
+- **Grouped wd / AdamW: neutral.** Optimizer state digital-side per standing doctrine.
+- **z-loss: win, free.** Zero analog hardware (only changes the top nudge signal); its FUNCTION —
+  keeping logits bounded — trains the network into analog range compliance.
+**EP two-phase check: NO new non-reciprocal element.** All four new pieces have symmetric-or-orthogonal
+Jacobians whose transposes reuse the same hardware (RMS/QK-norm self-transpose; RoPE = negative-angle
+same-mixer; gate-multiply transpose = multiply by the partner signal). Non-reciprocity remains confined
+to attention QKV coupling + crossbar transpose reads. PAR wall unchanged.
+**Honest new E-tier tolerance line-items:** (1) ~2x normalizer count (4/block + final): divider
+mismatch/offset sensitivity; (2) SwiGLU's 1408-wide Gilbert gate: per-multiply mismatch/noise;
+(3) RoPE phase error (expect very tolerant — phase error ~ position blur).
+Narrative gift: "the architecture the digital world adopted for training stability is the architecture
+analog needs for dynamic range."