diff options
| author | Yuren Hao <yurenh2@illinois.edu> | 2026-07-17 15:44:10 -0500 |
|---|---|---|
| committer | Yuren Hao <yurenh2@illinois.edu> | 2026-07-17 15:44:10 -0500 |
| commit | 07c585a5233023164c1193835885ea02e6cf1c41 (patch) | |
| tree | 4d8ce0e8e49e60f0c36444e242351f8754d61346 /hw_sim/NOTES.md | |
| parent | 1f8145768b77e2171e27fef33bc683e5a453beb6 (diff) | |
hw_sim: bus-settle fix menu parked as Dillavou session question (incl user's precharge-rotation idea)
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_014FAPDWQ49M5Ye3NpTndTpn
Diffstat (limited to 'hw_sim/NOTES.md')
| -rw-r--r-- | hw_sim/NOTES.md | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/hw_sim/NOTES.md b/hw_sim/NOTES.md index ace5528..bb616f5 100644 --- a/hw_sim/NOTES.md +++ b/hw_sim/NOTES.md @@ -21,3 +21,14 @@ DESIGN OPTIONS to clear the commit gate (for Dillavou session): (c) accept 3.14 us: wall-clock 9-14 d -> ~5% slip, not a cliff. NEXT (v1.1): resistor-mismatch Monte Carlo -> ENOB-after-cal proxy; op-amp noise integration vs contrast floor; then stage C = SPICE-in-the-loop EP training (8x8 toy). + +## OPEN QUESTION FOR THE DILLAVOU SESSION (user-parked, 2026-07-17) +Bus-capacitance settle (the v1 finding): naive 64-on-one-bus = 5.4 nF -> 16.6 us (killed). +Candidate fixes to put to the experts, in our preference order: + (b) bus segmentation 2x32 + dual TIA, digital sum (~2.2 us, no new parts) — current favorite; + (a) faster TIA (OPA356-class 50 MHz, $1-2) (~1.4 us); + (user idea) time-multiplexed bucket rotation with discharge/precharge phases — maps to real + segmented-bus + precharge techniques; feasibility/complexity tradeoff = expert question; + (c) accept 3.14 us (5% schedule slip). +None of this blocks the sim line: v1.1 (mismatch MC / ENOB, noise integration) and stage C +(SPICE-in-the-loop toy training) proceed independently of which fix wins. |