Initial commit: ept — backprop-free equilibrium transformer (EP)

Code (ep_run/), organized docs (docs/{method,campaign,hardware,outreach,paper}),
analysis scripts (scripts/), ONBOARDING.md entry point. Large data/checkpoints
git-ignored (share separately).

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_014FAPDWQ49M5Ye3NpTndTpn

1 files changed, 103 insertions, 0 deletions

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+[
+ {
+  "claim": "Naresh Shanbhag's UIUC DIMA line produced a fabricated 65nm SRAM-CIM test-chip that is the closest named-group match for an EP demo because it does BOTH analog/mixed-signal in-memory MVM AND genuine on-chip in-situ weight update. The chip (Gonugondla/Kang/Shanbhag, JSSC 2018, 'A Variation-Tolerant In-Memory ML Classifier via On-Chip Training') implements a Deep In-Memory Architecture SVM on a standard 16kB 6T SRAM array, computing the dot product W^T X via 'functional read' (PWAM word-line pulses generate a bit-line discharge proportional to a weighted sum), column-pitch-matched bit-line processors doing signed multiplication, and charge-sharing aggregation. It has a dedicated on-chip digital trainer that computes SGD gradients from on-chip inference and writes updated weights back into the SRAM array each batch (converging from random init to within 1% of floating-point in ~400 batches). In-situ training yields a concrete benefit: it lets the chip run at 38% lower bit-line swing (320mV vs 520mV) at iso-accuracy, a 2.4x IM-CORE energy reduction vs an off-chip-trained DIMA.",
+  "confidence": "high",
+  "sources": [
+   "http://shanbhag.ece.illinois.edu/publications/sujan-jssc-2018.pdf"
+  ],
+  "evidence": "Four unanimous 3-0 claims [0,1,2,3] all grounded in the primary JSSC 2018 paper (text extracted directly via pdftotext by verifiers). Abstract: 'a robust deep in-memory machine learning classifier with a stochastic gradient descent (SGD)-based on-chip trainer using a standard 16 kB 6T SRAM array... 65 nm CMOS prototype IC... on-chip trainable support vector machine.' Architecture has 'IM-CORE' (inference) + 'digital trainer' that 'writes the updated weights once per batch into the BCA'. Datapath: functional read -> BLP signed multiply -> CBLP charge-sharing -> W^T X. Energy: '38% lower VBL,max = 320 mV... reduction in IM-CORE energy by 2.4x at iso-accuracy.' This is the ONLY named-group chip combining analog MVM + on-chip gradient-based weight write-back.",
+  "vote": "3-0 (all four constituent claims)"
+ },
+ {
+  "claim": "Caveat on Shanbhag's match: the on-chip-trainable DIMA chip is a single-layer SVM binary/linear classifier with batch-mode SGD, not a deep multilayer or equilibrium/recurrent network. It demonstrates the two EP-critical mechanisms (analog in-memory MVM + per-batch on-chip weight write-back) but lacks a native settling/feedback (relaxation) loop and multilayer credit assignment; an EP equilibrium-transformer demo would need to add the relaxation dynamics and local two-phase update rule on top of this substrate.",
+  "confidence": "high",
+  "sources": [
+   "http://shanbhag.ece.illinois.edu/publications/sujan-jssc-2018.pdf"
+  ],
+  "evidence": "Verifier notes on claims [1] and [3] explicitly flag: 'it is a single-layer SVM with batch-mode SGD, not a deep multilayer trainer' and 'the demo is an SVM classifier on 6T SRAM-CIM, not an NN/transformer.' The chip proves on-chip SGD gradient computation + per-batch weight write, which is the load-bearing capability for EP-style local updates, but not the equilibrium/settling dynamics themselves.",
+  "vote": "3-0"
+ },
+ {
+  "claim": "Shanbhag's group also produced the C3SRAM macro (with ASU; Jiang/Yin/Seo/Seok, ESSCIRC 2019 + JSSC 2020), a fabricated 65nm SRAM in-memory-computing macro using analog-mixed-signal capacitive-coupling computing to do fully parallel XNOR-and-accumulate vector-matrix multiplication in a single cycle with one ADC per column \u2014 BUT it is INFERENCE-ONLY for binary (1-bit) weights/activations, with no on-chip training or in-situ weight update.",
+  "confidence": "high",
+  "sources": [
+   "https://www.researchgate.net/publication/336711317_C3SRAM_In-Memory-Computing_SRAM_Macro_Based_on_Capacitive-Coupling_Computing"
+  ],
+  "evidence": "Two unanimous 3-0 claims [4,5]. JSSC 2020 abstract: 'analog-mixed-signal (AMS) capacitive-coupling computing... binary-multiply-and-accumulate... one ADC per column... fully parallel vector-matrix multiplication in a single cycle... prototyped in 65-nm CMOS' (671.5 TOPS/W, 98.3% MNIST, 85.5% CIFAR-10). Targeted WebFetch of the paper confirmed 'a purely inference-accelerator system, not an on-chip training platform... does not support on-chip training, weight gradient computation, or in-situ learning.' A search snippet suggesting in-situ updates was confirmed to conflate a DIFFERENT (Meng-Fan Chang) macro. So C3SRAM provides analog MVM but fails the EP in-situ-update requirement.",
+  "vote": "3-0 (both constituent claims)"
+ },
+ {
+  "claim": "Yingyan Celine Lin is a UIUC ECE PhD (2017), was at Rice 2017-2022, and is now Associate Professor in the School of Computer Science at Georgia Tech \u2014 i.e. 'Yingyan Lin/Zhu at UIUC' refers to a UIUC-trained researcher now at Georgia Tech, NOT current UIUC faculty, and the surname is Lin, not Zhu. Her group does digital-accelerator/hardware-aware co-design and Digital-CIM (DCIM), with NO evidence of fabricated analog/mixed-signal, SRAM-analog-CIM, RRAM/memristor, or in-situ-trainable silicon; her venues are ML/architecture/EDA (MICRO/ISCA/HPCA/DAC/ICLR), not analog/circuits (ISSCC/VLSI/JSSC/Nature Electronics). She is therefore a poor fit to host the analog-equilibrium hardware an EP demo needs.",
+  "confidence": "high",
+  "sources": [
+   "https://www.cc.gatech.edu/people/yingyan-celine-lin"
+  ],
+  "evidence": "Two unanimous 3-0 claims [6,7]. GT page: PhD 'in Electrical and Computer Engineering from the University of Illinois at Urbana-Champaign in 2017... Assistant Professor at Rice University from 2017 to 2022... currently Associate Professor in the School of Computer Science.' dblp (pid 120/6981) confirms ZERO ISSCC/JSSC/VLSI/Nature-Electronics publications. Closest hardware works are DIGITAL: 'Fusion-3D' (MICRO 2024, taped-out 28nm DIGITAL NeRF accelerator) and '3DGauCIM' (explicitly Digital-CIM). No fabricated analog/RRAM/in-situ-trainable silicon attributed to her EIC lab.",
+  "vote": "3-0 (both constituent claims)"
+ },
+ {
+  "claim": "USTC's Tao Chen (\u9648\u6d9b) is a Special Professor (\u7279\u4efb\u6559\u6388) in the School of Microelectronics at USTC doing device/materials-level 'unconventional information processing' / in-materio reservoir computing \u2014 disordered dopant-atom networks in silicon (lead author of Nature 2020 'Classification with a disordered dopant-atom network in silicon', done at U. Twente), sulfonated-polyaniline reservoir networks, graphene devices. He does NOT build SRAM-CIM, RRAM arrays, ADC/DAC, or switched-capacitor circuit test-chips, and does NOT do EP hardware. His substrate is device-physics, not circuit-level CIM, so it is not a match for hosting an EP equilibrium-transformer demo.",
+  "confidence": "high",
+  "sources": [
+   "https://faculty.ustc.edu.cn/tchen/en/index.htm"
+  ],
+  "evidence": "Two unanimous 3-0 claims [12,13]. Faculty page: 'Special Professor (\u7279\u4efb\u6559\u6388)... School of Microelectronics... exploring the essence of intelligence and developing unconventional information processing technology' via 'multi-degree-of-freedom physical systems.' Flagship: Nature 577, 341-345 (2020) dopant-network classifier (nonlinear electron-hopping as physical reservoir). Targeted searches for RRAM/SRAM-CIM/ADC-DAC/switched-cap test-chips by this Tao Chen returned nothing; the 'graphene memristor' hits belong to other authors. Confirms the user's premise that he does hardware but not EP/CIM circuit hardware.",
+  "vote": "3-0 (both constituent claims)"
+ },
+ {
+  "claim": "The Stanford targets Wong and Raina (with UCSD's Gert Cauwenberghs, plus Tsinghua/Notre Dame/Pittsburgh) co-built the NeuRRAM chip (Wan et al., Nature 608:504-512, 2022): a fully-integrated RRAM/memristor compute-in-memory chip (48 cores, ~3 million RRAM cells + CMOS neurons) that performs analog in-memory matrix-vector multiplication \u2014 exactly the analog MVM primitive an EP equilibrium network needs. This establishes a fabricated, EP-relevant analog substrate from the named Stanford group, and a plausible collaboration target for a student.",
+  "confidence": "high",
+  "sources": [
+   "https://www.nature.com/articles/s41586-022-04992-8",
+   "https://web.stanford.edu/~hspwong/"
+  ],
+  "evidence": "Four unanimous 3-0 claims [8,10,11] (plus the inference-only caveat in [9]). Nature paper: '3 million RRAM devices... monolithically integrated with CMOS... 48-core RRAM-CIM hardware... in-memory matrix-vector multiplication.' Author list spans Stanford (Wong, Raina), UCSD (Cauwenberghs), Tsinghua (Huaqiang Wu), Notre Dame (Joshi/Schaefer), Pittsburgh (Kubendran). Official Stanford EE page titled 'Priyanka Raina and H.S. Philip Wong's NeuRRAM chip.' 130nm foundry process, real silicon. This is the strongest analog-MVM substrate among the named groups.",
+  "vote": "3-0 (all constituent claims)"
+ },
+ {
+  "claim": "Critical limitation: NeuRRAM is INFERENCE-ONLY and does NOT satisfy the EP in-situ local-weight-update requirement. Weights are trained off-chip in software and programmed onto the RRAM via incremental-pulse write-verify; the only on-hardware adaptation is 'chip-in-the-loop progressive fine-tuning' where the chip runs only the forward pass while backpropagation/weight updates run in software off-chip. So Stanford/Wong-Raina provide the analog MVM primitive but NOT native on-chip learning.",
+  "confidence": "high",
+  "sources": [
+   "https://www.nature.com/articles/s41586-022-04992-8"
+  ],
+  "evidence": "Unanimous 3-0 claim [9]. Nature paper: 'chip-in-the-loop progressive model finetuning, which uses the chip to perform the forward-pass one layer at a time during the back-propagation fine-tuning.' Weights set via 'incremental-pulse write-verify technique' \u2014 no on-chip learning rule. Corroborated by IEEE Brain ('AI Inference' chip) and UCSD/Stanford press ('Future versions will be able to learn'). IMPORTANT for the synthesis: a claim that Wong's group has demonstrated on-chip/in-situ weight update (RRAM gain-cell, IEDM 2024) was REFUTED 0-3, and an ISSCC-2020 74-TOPS/W RRAM test-chip attribution was refuted 1-2 \u2014 so do not over-credit Stanford with in-situ training.",
+  "vote": "3-0"
+ },
+ {
+  "claim": "Industry/analog in-memory vendor TetraMem (Qiangfei Xia / J. Joshua Yang, USC/UMass Amherst) ships a real fabricated memristive SoC, the MX100: 10 memristive computing cores each with a 248x256 1T1R RRAM/memristor crossbar in 65nm CMOS + RISC-V (Nature Electronics 2025). But it is INFERENCE-ONLY: networks are trained offline externally and the trained weights are mapped/programmed onto memristor conductances (closed-loop programming is write-verify of pre-computed weights, not gradient-based learning). It does NOT meet the EP local on-chip weight-update requirement. This also disambiguates the RRAM-SoC work as TetraMem/Xia/Yang, not USTC's Tao Chen.",
+  "confidence": "high",
+  "sources": [
+   "https://www.nature.com/articles/s41928-025-01409-y"
+  ],
+  "evidence": "Two unanimous 3-0 claims [14,15]. Nature Electronics 2025 'Radiofrequency signal processing with a memristive system-on-a-chip': '10 memristive computing cores... 65-nm CMOS... 248x256 1T1R crossbar.' Co-author Yi Huang's first-party post confirms 10 cores + 1T1R + RISC-V. Inference-only: sibling MX100 paper (arXiv 2410.14882) states 'weights were trained using a quantization-aware training method and subsequently converted to int8... transferred to the NPUs.' Vendor positions it for 'energy-efficient AI inference.' Mar-2026 currency check: still framed as 'AI inference chips' \u2014 no on-chip-training announcement.",
+  "vote": "3-0 (both constituent claims)"
+ },
+ {
+  "claim": "The in-situ on-chip-training capability EP needs currently exists primarily as research test-chips, not commercial product. A representative example: a fabricated 28nm CMOS Hybrid-Stochastic-Neuron (HSN) chip integrated with a 32x32 TiOx-based memristor VMM crossbar (Neurocomputing/Elsevier 2025, S0925231225031972, NRF Korea) performs FULLY IN-SITU training \u2014 the memristor VMM does forward propagation while the CMOS HSN chip runs backpropagation (gradient calculation AND weight updates) directly in hardware, host-free (demonstrated MNIST 94.13%, CIFAR-10 79.88%, 1.78 TOPS). This is an on-chip-trainable analog/mixed-signal system at small (32x32) RRAM test-chip scale \u2014 the architectural template closest to EP's in-situ-learning requirement, though it implements backprop, not EP.",
+  "confidence": "high",
+  "sources": [
+   "https://www.sciencedirect.com/science/article/abs/pii/S0925231225031972"
+  ],
+  "evidence": "Two unanimous 3-0 claims [17,18]. Abstract: 'Fabricated using 28 nm CMOS technology, the HSN chip integrates with a 32x32 TiOx-based memristor vector matrix multiplication (VMM)... performing backpropagation computations, including gradient calculation and weight updates, directly in hardware to eliminate external dependencies.' 'In-situ training operations were successfully demonstrated.' Caveat: 'analog' is loose (mixed-signal CMOS + analog memristor VMM), and full-CNN figures are chip+simulation system-level, not fully silicon-measured end-to-end. Demonstrates that on-chip gradient + weight update on a memristor crossbar is achievable today at test-chip scale.",
+  "vote": "3-0 (both constituent claims)"
+ },
+ {
+  "claim": "A practical path for a lab to build its OWN in-situ-trainable EP test-chip is foundry RRAM/MPW access: SkyWater's S130 (130nm volume-production CMOS) now offers a Weebit Nano ReRAM IP module (256Kb ReRAM array + control logic, decoders, IOs, ECC; fully JEDEC/AEC-Q100 qualified June 2023), explicitly positioned first for analog/mixed-signal applications, and SKY130 is the industry's first open-source foundry PDK (Apache 2.0, June 2020) based on a real commercially-manufactured node. This gives a research lab accessible embedded RRAM + an open PDK to tape out a custom analog-CIM/EP test-chip via MPW.",
+  "confidence": "medium",
+  "sources": [
+   "https://www.skywatertechnology.com/weebit-nano-reram-ip-now-available-in-skywater-technologys-s130-process/",
+   "https://www.skywatertechnology.com/sky130-open-source-pdk/"
+  ],
+  "evidence": "Claims [19] (3-0), [21] (3-0), and [20] (2-1). SkyWater/Weebit press (Mar 2023): S130 module 'includes a 256Kb ReRAM array, control logic, decoders, IOs... and error correcting code (ECC)' for 'analog/mixed-signal, IoT, automotive, industrial, and medical.' SKY130 = 'the industry's first open-source foundry Process Design Kit... based on SkyWater's volume 130 nm CMOS technology' (corroborated by FOSSi Foundation, Hackaday, GSA). Confidence MEDIUM (not high) because the analog-positioning claim [20] split 2-1, and the key CAVEAT (flagged by verifier): foundry 'analog/mixed-signal' marketing means embedded digital 1T1R NVM ON analog SoCs, NOT that this IP itself performs analog in-memory MVM or supports the multi-level analog-conductance weight tuning EP would ultimately need. So it is a substrate to BUILD on, not turnkey EP hardware.",
+  "vote": "3-0 (S130 RRAM IP, SKY130 PDK); 2-1 (analog/mixed-signal positioning)"
+ },
+ {
+  "claim": "There is no fabricated EP equilibrium-transformer hardware demo in the verified evidence; the only directly-EP-on-hardware work found is circuit-level SPICE simulation, not silicon. 'Memristor Crossbar Circuits Implementing Equilibrium Propagation for On-Device Learning' (Oh et al., Kookmin University, MDPI Micromachines 2023) is a Cadence Spectre / Ngspice / Verilog-A simulation study using a behavioral memristor model fit to other groups' device curves \u2014 there is no taped-out chip or physical crossbar. This frames the collaboration as net-new hardware work: the EP-specific two-phase local update has been simulated but not fabricated.",
+  "confidence": "high",
+  "sources": [
+   "https://www.ncbi.nlm.nih.gov/pmc/articles/PMC10384638/"
+  ],
+  "evidence": "Unanimous 3-0 claim [16]. Paper states results are 'simulated and verified' using 'CADENCE SPECTRE', 'Ngspice and Python', 'CADENCE GPDK 45-nm CMOS parameters'; memristor is a Verilog-A behavioral model. No fabricated chip/tape-out/measured results. Additionally, a claim that this work computes free-phase and nudge-phase EP solutions simultaneously in analog circuits was REFUTED 0-3. So EP-on-hardware remains pre-silicon; an EP equilibrium-transformer demo would be a first-of-kind fabrication built on one of the above substrates.",
+  "vote": "3-0"
+ }
+]
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