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diff --git a/CLOCKLESS_ANALOG_MVP_PLAN.md b/CLOCKLESS_ANALOG_MVP_PLAN.md new file mode 100644 index 0000000..522dc8c --- /dev/null +++ b/CLOCKLESS_ANALOG_MVP_PLAN.md @@ -0,0 +1,445 @@ +# Clockless analogue MVP for physical EP research + +**Prepared:** 2026-07-11 +**Starting point:** `COMPONENT_HW_MAP.md` +**Scope:** academic prototype, not a product demonstrator; analogue learning core; no processor, ADC, DAC, FPGA, sample-and-hold bank, phase clock, or digital optimizer in the learning loop. + +--- + +## 1. Executive decision + +The current `$5k–$20k` Demo-0 is not an MVP. It is an architecture demonstrator that tries to validate, at once, an SRAM-CIM module, bidirectional transpose reads, RoPE mixers, QK/RMS normalization, analogue softmax, SwiGLU multipliers, analogue state handling, ADC/DAC boundaries, a phase sequencer, write programming, and digital supervisory logic. A failure would be difficult to attribute to one mechanism. + +The lower-risk research question is narrower and more publishable: + +> Can a reciprocal nonlinear analogue network continuously learn by a local equilibrium contrast, with the free and nudged states physically present at the same time, without a clock or processor in the learning loop? + +Build that first. The recommended core is a **twin-equilibrium analogue learning tile**: + +- two small physical replicas of the same reciprocal nonlinear resistor network; +- corresponding trainable edges share one analogue weight capacitor; +- both replicas run continuously, so there are no sequential free/nudged phases; +- an output OTA supplies a true EP-style current nudge; a jumper also provides a voltage-clamped Coupled Learning control condition; +- each edge updates its own capacitor from a local contrast; +- manual boundary-condition selection and a manual learn/freeze switch replace an FPGA; +- a scope or DMM may observe the circuit but is not part of the feedback or learning path. + +Recommended first populated board: **8 sign-update edges plus one exact multiplier reference channel**, approximately **$170–$300** excluding instruments, tax, and shipping. This is about **17×–118× below** the current `$5k–$20k` board class. A one-edge calibration rig is approximately **$70–$130**. + +--- + +## 2. What “completely analogue and clockless” can honestly mean + +A defensible claim is: + +> The state evolution, nudge, local learning rule, and weight storage are continuous-time analogue processes. No periodic control signal, processor, converter, sampled state memory, or digitally computed parameter update participates in learning. + +Allowed outside the claim: + +- a bench supply; +- an oscilloscope or DMM used only for observation; +- a human changing input/target switches; +- a static mechanical learn/freeze switch; +- offline analysis after an experiment. + +A full language-model demonstration cannot honestly be entirely analogue and clockless at the token interface: symbol lookup, presentation of a sequence, cross-entropy labels, and token sampling are discrete operations. The academic MVP should therefore validate the **physical learning primitive**, then add a very small reciprocal attention cell as a second experiment. + +--- + +## 3. Core topology + +```text + analogue input x analogue target y* + │ │ + ┌────────────┴────────────┐ │ + │ │ │ + ▼ ▼ │ + FREE reciprocal network NUDGED reciprocal network + natural RC settling natural RC settling + output y0 output yβ + nudge current + │ ▲ │ + │ │ OTA/error transconductor + │ └──────────────┘ + │ + for every trainable edge e: + + edge voltage Δv0,e edge voltage Δvβ,e + │ │ + └──── local contrast cell ─────┘ + │ + charge/discharge current + │ + shared weight Cw,e + │ + ┌────────────┴────────────┐ + ▼ ▼ + MOSFET edge in free net MOSFET edge in nudged net +``` + +The two replicas must be laid out symmetrically and use matched transistor pairs where practical. The shared capacitor ensures both edge copies always use the same learned weight. + +### 3.1 State dynamics + +The node voltages are the states. Resistors/MOSFET conductances and node capacitances produce the relaxation automatically. Add small capacitors only where needed to set a reproducible pole and suppress oscillation; do not build a capacitor-plus-OTA integrator for every abstract model state. + +Design target, not a theorem: + +\[ +\tau_{weight}/\tau_{state} \ge 10^2, \quad \text{preferably }10^3. +\] + +The state should equilibrate much faster than the weight capacitors move. This time-scale separation replaces a settle detector and phase sequencer. + +### 3.2 True EP nudge and the CL control + +Populate both modes on the same board. + +**EP mode — current/force nudge.** For voltage outputs, compute the output error and inject a proportional current at the nudged output. A practical small-nudge implementation is + +\[ +I_\beta = -g_\beta\,(y_0-y^*) +\] + +with an LM13700-class OTA or a discrete transconductor. The polarity is chosen to push the nudged output toward the target. This crosses voltage error with current nudge and is the mode to use for the formal EP/gradient-flow claim. + +**CL mode — voltage constraint.** Buffer a weighted voltage between the free output and the target and impose it on the second replica. This is easier and reproduces the demonstrated clockless Coupled Learning architecture, but it should not be called exact EP. + +A two-position switch should select EP-current or CL-voltage nudge. That comparison is itself a useful experiment. + +### 3.3 Exact local contrast + +For a conductance-like parameter, the local energy derivative is proportional to the squared voltage drop. Use + +\[ +C_{w,e}\,\dot V_{w,e} + = s_e k\left[(\Delta v_{\beta,e})^2-(\Delta v_{0,e})^2\right], +\] + +where `s_e = ±1` accounts for whether increasing capacitor voltage increases or decreases effective conductance. + +Do not square twice. Use + +\[ +a^2-b^2=(a-b)(a+b), +\] + +so one four-quadrant multiplier can implement an exact reference channel. The established laboratory circuit used an AD633 with op-amp conditioning and a local capacitor. + +### 3.4 Low-cost sign contrast + +The exact multiplier dominates cost. A much cheaper local rule is + +\[ +C_{w,e}\,\dot V_{w,e} + = s_e I_0\;\mathrm{sgn}\left(|\Delta v_{\beta,e}|-|\Delta v_{0,e}|\right) +\] + +outside a deadband `δ`, with zero current inside the deadband. Implement it with absolute-value/rectifier stages, a comparator with hysteresis, and two matched charge/discharge current sources. + +This rule has precedent in simulated memristor EP hardware because it removes the analogue multiplier. The **continuous capacitor implementation proposed here is an engineering adaptation**, not an already demonstrated result. That is a legitimate research contribution, but it must be labeled correctly. + +### 3.5 Freeze and retention + +Use a mechanical toggle or relay to disconnect update current from every weight capacitor. Avoid a clocked switch matrix. Use film capacitors initially; characterize leakage and dielectric absorption. Volatile analogue weights are acceptable for an academic demonstrator, but not for a storage product. + +--- + +## 4. Recommended hardware ladder + +### Rung A — one-edge metrology tile + +Purpose: validate the physics before assembling a network. + +Populate: + +- one free/nudged MOSFET pair; +- one shared weight capacitor; +- one exact AD633 contrast path; +- one sign-only contrast path selectable by jumper; +- one EP-current nudge OTA; +- one CL-voltage nudge path; +- test points for all four edge terminals, multiplier inputs/output, capacitor current, and weight voltage. + +Estimated cost: **$70–$130**. + +Required measurements: + +1. transfer surface `I_update(Δv0, Δvβ)`; +2. exact-channel gain and offset; +3. sign-channel boundary, hysteresis, and deadband; +4. zero-contrast drift at `Δv0 = Δvβ`; +5. weight retention with learning frozen; +6. temperature drift; +7. nudge linearity versus `β`; +8. time-scale ratio between node settling and weight motion. + +Do not build the multi-edge board until this tile gives a stable null at zero contrast. + +### Rung B — two modular four-edge cards + +Build a four-edge card and populate two cards for eight trainable edges. Each card contains: + +- four twin MOSFET edges; +- four sign-update cells; +- four weight capacitors; +- local trim/deadband points; +- a shared learn/freeze bus that is static, not clocked; +- edge terminals on headers so the network topology is patchable. + +Recommended population: eight sign channels plus **one parallel exact AD633 channel on a selected edge**. This gives a continuously measured exact-versus-sign comparison without buying eight multipliers. + +Estimated cost: **$170–$300**. + +Initial task: + +- one-input nonlinear regression with 4–8 manually selected static examples; +- then a two-input task after topology simulation and one-edge characterization. + +Do not promise XOR at eight edges. The published nonlinear clockless network used 32 twin edges for XOR. Design the card so eight identical four-edge modules can be stacked later. + +### Rung C — 32-edge replication-class network + +Use eight four-edge cards and the sign-update rule. This approaches the scale of the published nonlinear demonstration while avoiding 32 AD633 multipliers. + +Estimated cost: **$450–$900**. + +This is still below the low end of the original plan by approximately **5.5×–44×** and is large enough for a serious robustness and nonlinear-learning study. + +### Rung D — reciprocal attention microcell + +Only after Rungs A–C work, add a transformer-adjacent cell: + +- two tokens; +- one head; +- scalar or two-dimensional state; +- tied key/value or another explicitly energy-based reciprocal construction; +- hardwired causal connectivity; +- no embedding memory, RoPE, RMSNorm, QK norm, SwiGLU, ADC, LM head, or token sampler. + +For two alternatives, softmax reduces to a logistic function of a score difference, so a differential pair can replace a general `N`-way entropic-resistor array. This is an **attention-shaped energy cell**, not an OLMo2 block. + +Estimated total including the learning core: **$300–$700**. + +--- + +## 5. Costed options + +Budgetary single-quantity catalogue prices checked on 2026-07-11; prices exclude tax, shipping, instruments, assembly labor, and rework. + +| Item | Planning role | Unit price used | Planning quantity, 8-edge board | Extended | +|---|---:|---:|---:|---:| +| ALD1106PBL | matched N-MOS array; two twin edges/package | $9.29 | 4 | $37.16 | +| AD633ANZ | exact four-quadrant contrast multiplier | $21.48 | 0, 1, or 8 | $0 / $21.48 / $171.84 | +| TLV274IPWR | quad rail-to-rail op amp | $1.43 | 6–8 | $8.58–$11.44 | +| LM13700 | dual OTA; output nudge/current sources | $1.70 | 1–2 | $1.70–$3.40 | +| LM339-class comparator | sign/deadband channels | about $0.67 | 2–4 | about $1.34–$2.68 | +| CD4066-class switch | optional static freeze/routing | about $0.73–$0.97 | 2–4 | about $1.46–$3.88 | +| Film capacitors | weight storage | about $0.63 at 1 µF | 8–12 | about $5–$8 | +| Diodes, resistors, trims | rectifiers, limits, biasing | — | lot | $15–$40 | +| PCB/protoboard, headers, test points | physical implementation | — | lot | $35–$120 | +| Power rails, protection, spare parts | laboratory overhead | — | lot | $30–$90 | + +Resulting envelopes: + +| Variant | Estimated build cost | Recommendation | +|---|---:|---| +| One-edge exact/sign calibration tile | $70–$130 | Build first | +| 8-edge sign-only | $140–$250 | Cheapest useful network | +| 8-edge sign + one exact reference channel | $170–$300 | **Recommended MVP** | +| 8-edge all-exact AD633 | $300–$500 | Only after reference channel works | +| 32-edge sign-update network | $450–$900 | Replication-class nonlinear demo | +| Reciprocal two-token attention add-on | +$100–$250 | Phase 2 only | + +### Aggressive transistor substitution + +A CD4007UBE costs about `$0.89` and contains a CMOS dual complementary pair plus inverter. It can be explored on the one-edge tile, but it is not the main-board recommendation: matching, body connections, and device operating region become the dominant uncertainty. Saving roughly `$30` of matched-transistor cost on an eight-edge board is not worth sacrificing the experiment’s interpretability. + +--- + +## 6. Delete list for the original plan + +For the academic MVP, delete these entirely: + +- SRAM-CIM, Mythic, HERMES, or other accelerator evaluation board; +- FPGA and phase sequencer; +- DAC and ADC arrays; +- token embedding lookup; +- RoPE DDS and mixers; +- full causal softmax array; +- QK normalization; +- RMSNorm banks; +- SwiGLU multiplier array; +- digital cross-entropy head; +- Adam/Muon or any digital optimizer; +- crossbar write-programming machinery; +- sampled free-phase memories; +- digital settle/retry logic; +- GPU gradient telemetry. + +Keep or replace as follows: + +| Original function | MVP replacement | +|---|---| +| MVM/crossbar | patchable reciprocal nonlinear resistor network | +| state integrators | natural RC/KCL state dynamics | +| sequential free/nudged phases | two continuously operating physical replicas | +| DAC nudge | OTA current injection | +| digital phase memory | simultaneous physical state comparison | +| outer-product update/programming | local capacitor charge/discharge | +| FPGA control | manual boundary selection and learn/freeze | +| ADC telemetry | buffered scope/DMM observation outside loop | + +--- + +## 7. Experimental matrix + +The cleanest paper is not merely “it learned.” It should isolate the choices that make the clockless implementation possible. + +### Factor 1 — nudge type + +- EP: voltage error, current nudge; +- CL: voltage error, voltage constraint. + +### Factor 2 — local update + +- exact difference of squares; +- sign-only magnitude comparison; +- sign-only with deadband/hysteresis. + +### Factor 3 — device quality + +- matched ALD1106 edges; +- one-edge CD4007 substitution; +- deliberate mismatch or trim-offset injection. + +### Factor 4 — nudge magnitude + +- small nudge; +- moderate/overclamped nudge; +- measured bias-versus-SNR curve. + +### Factor 5 — operating conditions + +- temperature; +- supply variation; +- capacitor leakage/hold time; +- damaged or disconnected edge; +- topology size. + +Proposed acceptance criteria, to be declared before network training: + +1. no periodic control signal in the learning loop; +2. no processor, ADC, DAC, or stored free-phase sample used for an update; +3. exact reference channel has a stable zero-contrast null; +4. sign channel agrees with the exact channel on update direction in at least 95% of the specified operating grid; +5. frozen weights remain within the chosen tolerance over the measurement interval; +6. loss decreases consistently across multiple resets, with all failures reported; +7. EP-current and CL-voltage modes are labeled separately. + +--- + +## 8. Six-week execution plan + +### Week 1 — SPICE and one-edge schematic + +- simulate the MOSFET edge over the intended node/gate voltage range; +- choose `Cw`, update current, and state capacitance for at least 100× time-scale separation; +- simulate exact and sign contrast transfer surfaces; +- simulate OTA current nudge and output compliance; +- add hard rails on weight voltage. + +### Week 2 — one-edge breadboard + +- build only the exact path first; +- measure offsets and null drift; +- add sign path and deadband; +- add manual freeze; +- decide whether breadboard leakage is tolerable or proceed directly to PCB. + +### Week 3 — one-edge characterization + +- automate only measurement if desired; do not put automation in the learning loop; +- produce measured update-vector fields; +- identify the safe voltage region; +- lock component values for the modular card. + +### Week 4 — first four-edge card + +- symmetrical placement; +- dense test points; +- patchable node topology; +- one exact reference edge routed in parallel with its sign cell. + +### Week 5 — eight-edge network + +- build a topology selected by SPICE; +- train one static example, then 4–8 manually selected regression points; +- compare exact-reference and sign decisions continuously. + +### Week 6 — robustness and paper figures + +- CL versus EP; +- exact versus sign; +- mismatch and temperature; +- retention and drift; +- energy/power by function; +- scaling estimate to 32 edges and the reciprocal attention cell. + +--- + +## 9. Claims this MVP can and cannot support + +### It can support + +- a continuous-time analogue physical-learning core; +- clockless simultaneous free/nudged operation; +- local analogue weight storage and updates; +- processor-free learning after boundary conditions are applied; +- measured exact-versus-sign update behavior; +- measured EP-current-versus-CL-voltage behavior; +- nonlinear supervised learning in a small reciprocal network; +- a credible scaling BOM. + +### It cannot support + +- a full analogue OLMo2 block; +- ordinary independent-Q/K/V attention on a passive reciprocal network; +- end-to-end clockless language modeling; +- nonvolatile weights; +- a claim that the sign-only capacitor rule is exact EP; +- a claim that voltage-clamped Coupled Learning is identical to EP; +- production energy/area numbers derived from a breadboard. + +A passive reciprocal network avoids the adjoint/transposed-Jacobian problem by construction, but it also excludes normal non-reciprocal attention. The transformer connection must therefore use tied, energy-based attention or be deferred to an active-adjoint phase. + +--- + +## 10. Why this is the better academic MVP + +It tests one scientific claim at a time. Every expensive item in the original plan exists to preserve a nearly complete transformer block. That is appropriate after the physical learning primitive is established, not before it. + +The proposed sequence produces publishable intermediate results even if the final nonlinear task fails: + +- measured clockless local-gradient circuit; +- exact-versus-sign learning rule; +- EP-versus-CL physical comparison; +- mismatch-induced bias and its suppression; +- analogue weight retention and drift; +- modular scaling law; +- reciprocal attention microcell. + +The main recommendation is therefore: + +> Build the `$70–$130` one-edge tile, then the `$170–$300` eight-edge hybrid board. Do not purchase a CIM evaluation module, FPGA, DAC/ADC bank, or softmax hardware for the MVP. + +--- + +## 11. Primary references used + +1. Sam Dillavou et al., **“Machine Learning Without a Processor: Emergent Learning in a Nonlinear Electronic Metamaterial,”** arXiv:2311.00537v2 / PNAS (2024). Demonstrated a fully analogue, clockless nonlinear twin-resistor network; 32 twin edges; local capacitive learning; XOR and nonlinear regression. Its implemented rule is Coupled Learning. +2. Sam Dillavou et al., **“Understanding and Embracing Imperfection in Physical Learning Networks,”** arXiv:2505.22887v2 (2026 revision). Characterizes bias, limit cycles, and system-agnostic suppression of analogue learning imperfections. +3. Joshua A. McGinnis, Xinbo Li, and Yoichiro Mori, **“Coercivity and Local Convergence of Physical Learning in Linear Circuits,”** arXiv:2606.15443 (2026). Distinguishes EP’s force/current nudge from CL’s voltage constraint and analyzes their gradient-flow structure. +4. Seung-Hyun Oh et al., **“Memristor Crossbar Circuits Implementing Equilibrium Propagation for On-Device Learning,”** *Micromachines* 14(7):1367 (2023). Proposes simultaneous free/nudged networks and a sign-only fixed-step update to remove analogue multipliers; results are simulation-oriented for memristor programming. +5. I. M. Elfadel and J. L. Wyatt, **“The ‘Softmax’ Nonlinearity: Derivation Using Statistical Mechanics and Useful Properties as a Multiterminal Analog Circuit Element,”** NeurIPS 1993. Establishes reciprocal/passive circuit properties of an entropic softmax element. +6. **“How to Train Your Resistive Network: Generalized Equilibrium Propagation and Analytical Learning,”** arXiv:2602.03546 (2026). Gives a single-network projector-based route for linear resistive networks; useful as a future replica-reduction direction, not the first nonlinear build. + diff --git a/docs/hardware/COLLABORATOR_BRIEF.md b/docs/hardware/COLLABORATOR_BRIEF.md index 3728657..0ce68ea 100644 --- a/docs/hardware/COLLABORATOR_BRIEF.md +++ b/docs/hardware/COLLABORATOR_BRIEF.md @@ -1,46 +1,57 @@ -# Backprop-free analog training of a transformer — collaboration brief -**One-page ask for hardware-side collaborators · 2026-06-21 · Yuren Hao (UIUC)** +# Backprop-free training of transformers — results and a staged hardware program +**One-page brief for hardware-side collaborators · rev. 2026-07-12 · Yuren Hao (UIUC)** ## The idea in three sentences -We train a **transformer block as a physical equilibrium (fixed-point) system** using **Equilibrium Propagation -(EP)** — no backpropagation. The forward pass is a damped relaxation `z ← z + ε·F(z)` that **settles** to a fixed -point (on analog hardware, the settling *is* the physics — nearly free); the weight update is **local**, computed -from the contrast between a free settle and a slightly-nudged settle. This is exactly the computation an analog -in-memory / memristive array is good at — and unlike every shipping analog-AI chip (all inference-only), it needs -**in-situ weight update**, which is the open opportunity. +We train **standard multi-layer transformers** with **Equilibrium Propagation** on a layered energy: +training consists of two relaxation phases and a **local** contrast update per weight — no +backpropagation anywhere — and inference is an ordinary forward pass. On GPU this now works at +language-model scale with essentially no quality gap to backprop. The hardware program starts with +the cheapest object that can validate the physical learning rule — a **clockless twin-network +analog tile (~$300)** — and climbs rung by rung to an in-memory-compute transformer block. -## Why now / why it's real (not speculative) -- **Algorithm side (ours, in simulation):** EP's gradient matches true backprop (cosine ≈ 0.99–1.0 per component); - the equilibrium transformer trains stably and **matches/beats a same-parameter BP transformer** on language modeling. - Currently scaling the recipe; a fix for the one known instability (a residual-defense term) is under validation. -- **Hardware precedent exists:** local contrastive/EP learning has been physically demonstrated (self-learning analog - resistor networks, ~1 µs settling, on-chip weight update from a local free-vs-clamped difference; EP on a D-Wave - Ising machine). **But nobody has built an EP-trained *transformer* in analog hardware — that is the first-mover demo.** -- **Endurance clears the bar:** HfOx-class RRAM survives ~10^10 write cycles; a training run needs ≤10^8 device writes - (fewer with digital-accumulate-then-threshold-program). Endurance is not the blocker — update linearity/symmetry is - the real device challenge. +## GPU-scale results (2026-07, measured) +- **A 12-layer, 42.7M-parameter transformer LM trained for a full epoch (59k steps, 361M tokens) + with no backpropagation in the training loop; it generates coherent text.** To our knowledge the + first transformer language model trained fully this way. +- **Gap to a tuned, same-architecture backprop control: 0.05 nats** (at 4k steps: statistically + indistinguishable, 3 seeds/arm). Prior backprop-free attempts at scale all report qualitative gaps. +- EP step = **3.2× backprop FLOPs** (measured); mixed-precision training validated; the two known + EP-specific instabilities are mechanistically diagnosed and closed (an estimator-SNR floor with a + β-schedule law; a relaxation-contractivity crossing eliminated by norm placement). +- **Every trained operation chosen analog-implementable:** crossbar MVM, divisive normalization, + fixed I/Q rotations (position code), translinear gated MLP, subthreshold-exponential softmax, + two-phase relaxation for the learning rule. -## What a hardware demo needs (three layers) — and the UIUC ECE fit -| Layer | What it does | Closest collaborator | -|---|---|---| -| **Trainable device** | in-situ-updatable analog weights (RRAM/FeFET/ECRAM) — *the part you cannot buy* | **Wenjuan Zhu** (UIUC ECE, memristor/RRAM/FeFET/2D devices) | -| **In-memory MVM circuit** | analog matrix-vector multiply + on-chip weight write-back | **Naresh Shanbhag** (UIUC ECE) — his JSSC-2018 DIMA chip *already* does analog MVM **+ on-chip SGD weight write-back** in 65nm; nearest existing substrate | -| **Mixed-signal glue / control loop** | ADC/DAC to read settled states + apply the nudge; switched-cap integrators = relaxation primitives | **Pavan Hanumolu** (UIUC ECE, data converters / PLL / switched-cap) | -| **EP control + sim** | the settle→nudge→settle→local-Δθ loop, noise/endurance de-risk in simulation | **us** (FPGA + the trained model + analog-noise sim already built) | +## Measured fault tolerances (fault injection at the trained model) +| fault | free | marginal | dead | +|---|---|---|---| +| weight precision | **8-bit** (ΔCE +0.004) | 6-bit (+0.05) | 4-bit | +| forward state noise | **1%** | — | — | +| error-channel (nudge) noise | **10% relative** | 30% | — | +| divider mismatch / gate gain / phase error | 3% / 10% / 0.03 rad | 10% / — / 0.1 rad | — | -**Escalation / device frontier:** **H.-S. Philip Wong (黄汉森, Stanford EE / TSMC Chief Scientist)** — NeuRRAM (Nature -2022) is the most EP-relevant analog-MVM substrate (inference-only today); the RRAM-device heavyweight + a TSMC-foundry -path, reachable via a Stanford student contact. +Under every non-fatal fault the learning signal tracks the *faulted* network (gradient cosine ≈ 0.97 +invariant): **the rule co-adapts to the device.** The only hard spec is ~7-bit effective weights. -## The concrete ask (staged, modular — stitch existing capabilities, no startup-scale custom fab) -- **Phase 1:** put ONE equilibrium-transformer block on an existing in-situ-trainable substrate (Shanbhag's DIMA-class - chip + Hanumolu converter/integrator glue; Zhu devices) + our FPGA EP-control loop → prove end-to-end analog EP training. -- **Phase 2:** scale weights (foundry RRAM MPW — e.g. SkyWater S130 + Weebit ReRAM IP — or a fixed-weight inference array - for the forward path with the trainable layer in-situ). -- **What we bring:** the validated algorithm, the trained model + scaling data, the EP control logic, and a simulator - that already models analog non-idealities (device noise / quantization / asymmetric update) to de-risk before tape-out. +## The hardware ladder (each rung publishable alone) +1. **One-edge metrology tile ($70–130):** twin MOSFET edge, shared weight capacitor, exact + (difference-of-squares) and sign-only local update channels, OTA current nudge — no processor, + converter, clock, or sampled memory in the learning loop. +2. **8-edge twin network ($170–300):** nonlinear regression; EP current-nudge vs Coupled-Learning + voltage-clamp on one board; exact-vs-sign update comparison; measured bias-vs-nudge-magnitude + curve (the same β-SNR law we measured in simulation). +3. **32-edge network ($450–900):** replication-class nonlinear tasks, robustness study. +4. **Reciprocal attention microcell (+$100–250):** two tokens, one head, energy-based attention. +5. **CIM transformer block (partner phase):** analog MVM + in-situ two-phase EP weight update — + the piece no shipping analog-AI chip has (all are inference-only or on-chip-backprop). +6. **North star: a few-M-parameter TinyStories LM trained on analog hardware.** -**Bottom line:** the science is done in sim and the hardware pieces all exist in-house at UIUC ECE — this is a -stitching + first-demo opportunity, not a multi-year custom-silicon program. +## What we bring / what we ask +**Bring:** the trained models and recipe, the estimator theory (β-SNR law, stability walls), the +measured tolerance ledger, SPICE-first costed build plan, and parts funding (rungs 1–3 are <$1k). +**Ask (rungs 1–3):** bench access, analog-design mentorship, and/or a student who enjoys discrete +analog — six-week plan, instruments = a scope and a DMM. **Ask (rung 5):** a CIM/mixed-signal +partnership where the substrate expertise is yours and the learning rule is ours. -*(Backing detail + citations: HW_RESEARCH_FINDINGS.md; method: ept_method_intro.pdf)* +*(Detail: CLOCKLESS_ANALOG_MVP_PLAN.md — full BOM, schedule, acceptance criteria, claim limits; +COMPONENT_HW_MAP.md — per-operation analog mapping + tolerance status.)* diff --git a/docs/hardware/COMPONENT_HW_MAP.md b/docs/hardware/COMPONENT_HW_MAP.md index ff47123..0cae1ea 100644 --- a/docs/hardware/COMPONENT_HW_MAP.md +++ b/docs/hardware/COMPONENT_HW_MAP.md @@ -48,7 +48,12 @@ Companion docs: `HW_RESEARCH_FINDINGS.md` (softmax dossier, OLMo2 analog audit, ## D. Demo scoping (reuse-doctrine currency) -- **Demo-0 (spec target of E-tier):** single cascade block, SRAM-CIM eval module + FPGA harness + +- **⚡ 2026-07-12: Demo-0 SUPERSEDED as the first rung by CLOCKLESS_ANALOG_MVP_PLAN.md** + (user-authored): a $170–300 clockless twin-network tile (Dillavou-lineage; EP current-nudge vs CL + voltage-clamp; exact vs sign local update; no processor/converter/clock in the learning loop) + validates the physical learning primitive first. The CIM block below becomes the PARTNER rung + (rung 5 of the ladder in COLLABORATOR_BRIEF.md). +- **Demo-0 (now rung 5, partner phase):** single cascade block, SRAM-CIM eval module + FPGA harness + COTS mixer/DAC/ADC periphery; goal = demonstrate the two-phase θ-read on one block with measured tolerances. Board-BOM class: $5–20k. - **Demo-1:** time-multiplex ONE physical trainable block through L logical positions (cascade's diff --git a/docs/outreach/OUTREACH_TARGETS.md b/docs/outreach/OUTREACH_TARGETS.md index ffbd177..e4cfdad 100644 --- a/docs/outreach/OUTREACH_TARGETS.md +++ b/docs/outreach/OUTREACH_TARGETS.md @@ -1,4 +1,140 @@ -# EP analog-hardware collaboration — outreach targets (2026-06-21) +# EP analog-hardware collaboration — outreach targets (2026-06-21; REVISED 2026-07-12) + +## ⚡ 2026-07-12 REVISION — gate LIFTED, story changed by the clockless MVP +**User instruction 2026-07-12: outreach begins now.** Gate artifacts in hand: 42.75M full-epoch +"能看" demo (first BP-free transformer LM, gap 0.05 nats), E-tier tolerance ledger, cost model, +and **CLOCKLESS_ANALOG_MVP_PLAN.md** (user-authored) which replaces the $5–20k CIM Demo-0 with a +**$170–300 clockless twin-network tile** (Dillavou-lineage; EP-current vs CL-voltage on one board; +exact vs sign local update; no processor/converter/clock in the learning loop). + +**What the MVP changes about outreach:** +1. The ask shrinks from "help us engineer a CIM demonstrator" to "host/advise a $300, six-week, + scope-and-DMM bench build" — any analog lab can say yes. +2. The scientific lineage points at the **physical-learning community (Penn/Dillavou)**, not only + CIM-VLSI. Dillavou becomes a wave-1 target (his PNAS 2024 board is the design's ancestor; our + deltas: true EP current nudge, exact-vs-sign matrix, the LM program + β-SNR law transfer). + Affiliation note (checked 2026-07-12): LinkedIn = "Independent Researcher, ARIA R&D Creator"; + Penn pages still list postdoc (Durian/Liu). Email the Penn address; keep title-neutral wording. +3. Substrate groups (Shanbhag CIM, Zhu FeFET, THU, Stanford) are **rung-5 partners** (CIM block) — + still first-mover whitespace, pitched as the rung AFTER the tile, which makes us look staged + rather than speculative. Hanumolu's converter relevance drops (MVP deletes converters) → wave-2. +4. Shared quantitative hook everywhere: the board's Factor-4 (bias-vs-nudge-magnitude) = the wall-1 + β-SNR law we measured in fp32 + the E-tier error-channel result (10% relative noise free) — + "the same law, measured in simulation and in physics." + +**Revised sequencing:** wave-1a **Dillavou** (design review + natural collaborator; fastest +credible yes/no) → wave-1b **Shanbhag trio** (local bench + rung-5 CIM; E-tier speaks compute-SNR) +→ wave-2 Zhu (nonvolatile-weight rung: film cap → FeFET conductance), Hanumolu (rung-5 mixed-signal +glue), Mingu Kang, Stanford → unicorns (Grollier/Querlioz) once the 32-edge board exists. +**Ben/Rain thread stays separate** — the MVP plan flows there after the current Overleaf beat. + +**Attachments per send:** COLLABORATOR_BRIEF (rev. 2026-07-12, rewritten to cascade-era) + +CLOCKLESS_ANALOG_MVP_PLAN.md (Dillavou/Shanbhag) — render to PDF and VISUALLY VERIFY before send. +Sender-title TODO still open. Current drafts: §"Email drafts v2" below; the 2026-06-21 drafts at +the bottom are SUPERSEDED (looped-era framing, CIM-first ask). + +--- + +## Email drafts v2 (2026-07-12) — copy-paste after title/attachment check + +### Draft B (wave-1a) — Sam Dillavou · To: dillavou@sas.upenn.edu +Subject: A true-EP current nudge on a twin-network learning circuit — building on your PNAS design + +Hi Dr. Dillavou, + +I'm Yuren Hao (UIUC). Two results may interest you. On the algorithm side, we recently trained a +standard 12-layer transformer language model entirely without backpropagation — equilibrium +propagation on a layered energy, all updates local — to within 0.05 nats of a tuned backprop +control over a full epoch; it generates coherent text. On the hardware side, we are starting a +physical-learning build whose design descends directly from your processor-free network: two +continuously-running replicas, shared weight capacitors, local contrast updates, no clock or +processor in the learning loop. + +The planned departures from your architecture are the reason I'm writing. First, an OTA current +nudge alongside the voltage clamp, so EP's force nudge and Coupled Learning's constraint can be +compared on the same board — the distinction McGinnis, Li and Mori recently formalized. Second, one +exact difference-of-squares contrast channel running in parallel with sign-only update cells, for a +continuous exact-versus-sign comparison. Third, a measured bias-versus-nudge-magnitude curve: in +simulation we find the EP error channel tolerates 10% relative noise, while an additive precision +floor sets a hard threshold on the nudge amplitude — the board should exhibit the same law in +physics, and your imperfection-characterization paper is the closest existing treatment. + +Would you have 20–30 minutes to talk? We would value your judgment on the design before we commit +the board, and there may be a natural collaboration — we bring the transformer/LM program and the +simulation tolerance data; the physical-learning lineage is yours. A one-page brief and the build +plan are attached. + +Best, Yuren + +### Draft A (wave-1b) — Shanbhag group · To: Soonha Hwang (soonhah2@), Mihir Kavishwar (mihirvk2@) · cc: Shanbhag +Subject: Backprop-free transformer training — GPU-scale results and a staged path to CIM + +Hi Soonha and Mihir, + +I'm Yuren Hao, working on backprop-free training in ChengXiang Zhai's group at UIUC. The project +recently crossed a threshold worth reporting: we trained a standard 12-layer transformer language +model with equilibrium propagation — no backpropagation anywhere in training, every update local — +to within 0.05 nats of a tuned backprop control over a full epoch, and it generates coherent text. +Inference is an ordinary forward pass. Every operation in the recipe was chosen to have a known +analog implementation, and we have measured the fault tolerances the learning rule actually needs: +8-bit effective weights are lossless and 6-bit marginal; the error channel tolerates 10% relative +noise; 1% forward state noise costs nothing. + +We are deliberately starting the hardware small: a ~$300 clockless twin-network tile (descended +from the Penn processor-free learning circuits) that validates the physical learning rule with no +processor, converter, or clock in the loop. The reason to write to your group is the rung after +that: a CIM transformer block with in-situ EP updates — analog MVM plus a local two-phase weight +update. Your DiT accelerator and the compute-SNR ADC line are the closest existing substrate for +that rung, and the tolerance table above is, in effect, its SNR budget. + +Could I grab 20 minutes to show the results and the staged plan? A one-page brief is attached. +(cc'ing Prof. Shanbhag.) + +Thanks, Yuren + +### Draft C (wave-2) — Wenjuan Zhu · To: wjzhu@illinois.edu +Subject: Nonvolatile analog weights for a physical equilibrium-propagation learner — FeFET fit? + +Dear Prof. Zhu, + +I'm Yuren Hao, working on backprop-free training in ChengXiang Zhai's group at UIUC. We train +transformers with equilibrium propagation — no backpropagation; each weight updates from a local +contrast between two settled states — and recently demonstrated this at language-model scale in +simulation (a 12-layer model within 0.05 nats of its backprop control). We are now building a small +clockless analog learning network in which each weight is a capacitor charged by its own local +update circuit. + +The capacitor is the honest weakness: it is volatile. The natural upgrade is exactly your group's +territory — a nonvolatile, electrically-programmable, multilevel conductance, and your vdW / +CuInP2S6 FeFETs are the closest devices I know of. I realize that work has centered on memory and +logic rather than training; the question is whether a FeFET conductance could replace the weight +capacitor in a continuously-learning analog network, with the update current driving the gate. + +Would you have 20 minutes to discuss feasibility? A one-page brief and the build plan are attached. + +Best, Yuren + +### Draft D (wave-2) — Hanumolu · To: hanumolu@illinois.edu +Subject: Mixed-signal partner for the CIM phase of an analog learning program — student pointer? + +Dear Prof. Hanumolu, + +I'm Yuren Hao, working on backprop-free training in ChengXiang Zhai's group at UIUC. We train +transformers with equilibrium propagation (no backpropagation; local two-phase updates), recently +at language-model scale in simulation, and are starting the hardware side with a deliberately +minimal clockless analog tile — no converters at all in the learning loop. + +The phase where your group's expertise becomes central is the one after: an in-memory-compute +transformer block, where settled-state readout, nudge injection, and loop stability are +mixed-signal problems. Nearer-term, the tile itself has one control-loop question — enforcing a +100–1000× time-scale separation between state settling and weight motion — that a student who +enjoys discrete analog and feedback loops might find fun as a side project. + +Could you point me to a student for either, or spare 15 minutes? One-page brief attached. + +Best, Yuren + +--- Per-group PhD/PI profiles from 5 research agents. Accuracy discipline: emails only where published or netid on an official directory; "—" = not public, route via PI (no invented addresses). Verify "current" status before sending — students graduate. Companion: COLLABORATOR_BRIEF.md (the one-pager), HW_RESEARCH_FINDINGS.md (citations). @@ -133,7 +269,8 @@ world — EP-rich, mostly device-light. Pair one of each. --- -## ⏸ STATUS (2026-06-21): HOLD — DO NOT SEND until the 33M demo + scaling dossier +## ~~⏸ STATUS (2026-06-21): HOLD~~ → **GATE LIFTED 2026-07-12 (user instruction; artifacts delivered). Use "Email drafts v2" above; everything below is the superseded 06-21 record.** +## (superseded) ⏸ STATUS (2026-06-21): HOLD — DO NOT SEND until the 33M demo + scaling dossier **User decision (CONFIRMED 2026-06-21): outreach is gated on the ~33M "能看" demo + scaling-law dossier (task #15) — NOT the C512/2.09 milestone.** Send nothing until there's a readable-generation ("能看") demo + a scaling-law dossier to lead with. (C512 EP descending past the 2.09 wall toward ~1.8 is a prerequisite step that validates the recipe, NOT the outreach gate — @@ -141,7 +278,7 @@ the gate is the bigger, showable 33M artifact.) Until then: no contact with anyo When the bar is met: set sender title, render COLLABORATOR_BRIEF.pdf, attach + ept_method_intro.pdf, optionally ask Prof. Zhai for a warm intro to Shanbhag/Hanumolu first. All profiles/contacts/pairing/drafts above are durable and ready. -## Email drafts (READY, gated — copy-paste when the bar is met) +## Email drafts v1 (2026-06-21) — SUPERSEDED by v2 above (looped-era framing, CIM-first ask; kept for the record) ### Draft 1 — Shanbhag group · To: Soonha Hwang (soonhah2@), Mihir Kavishwar (mihirvk2@) · cc: Shanbhag Subject: Backprop-free (Equilibrium-Propagation) transformer training — a fit for your in-memory CIM work? |