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Diffstat (limited to 'docs/hardware/HW_RESEARCH_FINDINGS.md')
| -rw-r--r-- | docs/hardware/HW_RESEARCH_FINDINGS.md | 29 |
1 files changed, 26 insertions, 3 deletions
diff --git a/docs/hardware/HW_RESEARCH_FINDINGS.md b/docs/hardware/HW_RESEARCH_FINDINGS.md index e6b77b9..0a749db 100644 --- a/docs/hardware/HW_RESEARCH_FINDINGS.md +++ b/docs/hardware/HW_RESEARCH_FINDINGS.md @@ -248,6 +248,29 @@ concur). Per-parameter adaptivity (Adam-class) is empirically LOAD-BEARING for E ⟹ Revised chip narrative: **factored-Adam (AGC/Tiki-Taka route) is not the premium tier — it is the MANDATORY baseline**. The +2× analog memory and ~16C AGC channels per block are the price of admission for analog EP training, and the OmniOpt "Lion is cheap"路线 does not apply to us. -Muon stays priced out of analog (GPU/simulation-era tool). This RAISES the priority of the deferred -optimizer-state research (Tiki-Taka transfer constants, AGC channel specs, trace leakage — rerun -when API budget recovers): the analog-Adam engineering is now on the critical path of the chip story. +Muon stays priced out of FULLY-analog implementations (GPU/simulation-era tool). + +### CORRECTED ECONOMICS (2026-07-11 #2) — priced in the PROJECT DOCTRINE currency (reuse, NOT fab) + +**Retraction:** any tapeout/"$M program" framing in this session is VOID. The standing build +doctrine (this file, 2026-06-21 BOTTOM LINE + UIUC map) is: **COTS-stitch** (memristor CIM eval +module + FPGA carrying softmax/LN/optimizer/EP control) → Phase-2 **Mythic/HERMES-class COTS** for +bulk FIXED MVM → the un-buyable in-situ substrate via the **UIUC collaboration** (Zhu device fab + +Shanbhag DIMA-line CIM + Hanumolu converters), grant-funded. No startup silicon, ever. + +**The doctrine already settles the optimizer hardware question:** the verified update path is +**digital-accumulate → threshold-program** (bulk-switching template, 3-0) — every gradient +increment passes a DIGITAL accumulator by design (that IS the endurance fix). Hence optimizer +state lives digital-side (FPGA BRAM/DDR), not in analog: +- **Adam ≈ free**: m,v = 2 extra digital words/weight in memory the doctrine already requires. + Zero new analog components. (The per-synapse-cap / AGC-channel analysis above = appendix + curiosity for a fully-analog optimizer nobody asked for.) +- **Muon: not hardware-blocked at demo scale**: NS runs FPGA/host-side on the digitized gradient + stream (~24 GFLOP/step at C512×12 — trivial at Hz step rates). Its wall re-emerges only in + fully-analog ambitions. ⟹ **Adam-vs-Muon remains an ALGORITHM question (D1a's EP-Muon arm is + the referee), not a hardware question.** Lion/SGD stay algorithmically banned. + +**Demo-1 cost in doctrine currency:** CIM eval module + FPGA dev board + converter glue ≈ +**$5–20k board-level BOM + engineering time**; beyond-eval-kit in-situ arrays come from the UIUC +device/circuit line (their fab, grant money). GAP-2 procurement pass (TetraMem / Anadigm FPAA / +Aspinity SKU + prices) remains the open to-do it always was. |