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+# EP analog-hardware collaboration — outreach targets (2026-06-21)
+Per-group PhD/PI profiles from 5 research agents. Accuracy discipline: emails only where published or netid on an
+official directory; "—" = not public, route via PI (no invented addresses). Verify "current" status before sending —
+students graduate. Companion: COLLABORATOR_BRIEF.md (the one-pager), HW_RESEARCH_FINDINGS.md (citations).
+
+## The cross-cutting framing (true at EVERY group — this is our wedge)
+Every group has EITHER the analog substrate OR an on-chip-training piece — **none has backprop-free LOCAL
+in-situ update on analog weights**. The EP local-update rule is the genuinely new thing WE bring; everyone else
+does inference-only analog MVM, or on-chip *gradient/backprop* training. First-mover gap. Say it plainly.
+
+## Strategy
+PhD-first / cc-PI where there's a clear hands-on student; PI-direct where the group is small or no student fits.
+UIUC first (home turf, all 3 layers local). Stanford = Phase-2 warm intro via your student. THU = strongest
+substrate, hardest access.
+
+---
+
+## 1. Shanbhag (UIUC ECE) — LEAD. Route: PhD-first, cc Shanbhag. The closest existing substrate.
+His JSSC-2018 DIMA chip already did analog MVM + on-chip SGD weight write-back. Current bench is rich but no
+single student spans all of {analog-MVM substrate + settling + on-chip learning} — pitch the trio:
+- **Soonha Hwang** `soonhah2@illinois.edu` — HIGH, **email first**. Building a *transformer* mixed-signal CIM chip
+  (28nm DiT accelerator, ESSERC 2025); grad 2028 (multi-year runway). Owns substrate (a)+(b). Caveat: his chip reads
+  inference-only — in-situ weight update would be new (= our piece).
+- **Mihir Kavishwar** `mihirvk2@illinois.edu` (publicly listed) — HIGH. Analog-MVM + compute-SNR-optimal ADCs
+  (CACTUS, arXiv 2507.09776). The readout/SNR layer the equilibrium readout lives or dies on.
+- **Vignesh Sundaresha** `vs49@illinois.edu` — HIGH on the *learning* axis. GEARnn in-situ on-edge training
+  (arXiv 2410.07691). Caveat: algorithm-level, standard training (not EP, not yet a mixed-signal learning circuit).
+- Others: Shuo Li (postdoc, analog-CIM characterization — verify still here), Saion Roy (MRAM/resistive CIM + error
+  compensation — but drifting to security, see Hanumolu note), Kaining Zhou (CIM simulation framework, kainingz@).
+
+## 2. Mingu Kang (UC SAN DIEGO faculty) — the in-situ-update know-how that LEFT UIUC. Route: PI-direct (peer faculty).
+**Built the original DIMA on-chip-SGD-write-back substrate** we cite (PhD 2017 w/ Shanbhag), now PI at UCSD. The
+person who most owns "analog MVM + on-chip weight update" anywhere. Strong faculty-level collaborator specifically for
+the update-loop piece. (Sujan Gonugondla, the other DIMA-trainer author, → Amazon, industry.)
+
+## 3. Wenjuan Zhu (UIUC ECE) — device layer. Route: PI-DIRECT (small group, device experts graduated).
+Email **wjzhu@illinois.edu**. HONEST FRAMING: their ferroelectric work is **memory/logic (FeFET memory, CAM,
+reconfigurable transistors), NOT synaptic weight-update training** — fit is device-platform overlap (vdW / CuInP₂S₆
+FeFETs = nonvolatile, electrically-set, multilevel conductance). Pitch = "extend your FeFETs to in-situ analog
+training," do NOT imply they already do it. Name-drop:
+- **Junzhe Kang** `junzhek2@illinois.edu` — the CIPS-FeFET / in-memory-computing lead (ACS Nano 2024/2025). On the
+  graduation boundary (2024 dissertation, still publishing 2026) — verify status.
+- **Ye Lin** — current student on the CIPS platform (—, via PI). Alumni (now industry): Zijing Zhao→Apple, Hojoon Ryu→Intel.
+
+## 4. Hanumolu (UIUC ECE) — converter/control-loop glue. Route: PI-DIRECT (no student is a pure data-converter).
+Email **hanumolu@illinois.edu**, ask him to route. Reality: his group is a **clocking / high-speed-link / frequency-
+reference** shop, not a data-converter shop — no current PhD has ADC/DAC/switched-cap as primary thesis. Best fits if
+he points to a student:
+- **Mahmoud Khalil** `mkhalil4@illinois.edu` — best converter+loop match: sampling-PLL (ISSCC 2024, 1st author) +
+  industry ADC + DC-DC converter experience. The settle→nudge feedback loop is his native language.
+- **Sujay Patel** `sujaysp2@illinois.edu` — mixed-signal links/equalizers + recovery loops (CICC 2026).
+- **Jason (Shuozhen) Liu** `sl111@illinois.edu` (netid single-sourced, verify) — only one stating ADC focus, but junior/no papers.
+- NOTE: the most topically-relevant IMC+ADC person, **Saion Roy**, is **Shanbhag's** grad (now security postdoc @ Northeastern), NOT Hanumolu's — don't mis-target.
+
+## 5. Wong + Raina (STANFORD) — Phase-2 escalation. Route: WARM INTRO via your Stanford student.
+Stanford leads **foundry-RRAM-as-weights + on-chip training** (CHIMERA/MINOTAUR) + **NeuRRAM analog-MVM inference** —
+but NOT analog in-situ gradient programming (the EP piece is still ours).
+- **Jeffrey Yu** `jeffreyy@stanford.edu` (Raina, current) — PRIMARY. On-chip transformer fine-tuning w/ RRAM
+  (MINOTAUR; 8-bit transformer fine-tuning ISCA 2024). The bridge to "train a transformer on RRAM," still in the building.
+- **Shuhan Liu** (Wong, final-year — move fast) — RRAM device/array + edge continual training (IEDM 2024). Loop in for device side.
+- Refs (not resident): Kartik Prabhu (CHIMERA/MINOTAUR; prob. → Meta, verify), Weier Wan (NeuRRAM lead → CTO Aizip, industry consult).
+
+## 6. Tsinghua (THU) — strongest in-situ SUBSTRATE in the world, but backprop-family + hardest access.
+Wu/Gao/Qian LEMON lab + Jianshi Tang, School of Integrated Circuits. THE clear #1 for fabricated, system-integrated
+silicon that closes the weight-write loop ON-CHIP during learning — the inference-only barrier everyone else hits, they've
+crossed. BUT (the "not EP-flavored" point, confirmed sharply): every on-chip rule they've shipped is **backprop-family /
+NON-local** (Sign-Backprop [Gao et al., Neural Networks 2018]; STELLAR's sign-SGD), **MLP/CNN-scale, never a transformer,
+never EP**. Their only energy/attractor touchpoint is a 2015 Hopfield associative-memory (Hebbian recall, not training).
+⇒ clean whitespace: we'd bring the first local/EP rule + first in-situ transformer to the one group with write-capable silicon.
+- **Jianshi Tang (唐建石)** — **jtang@tsinghua.edu.cn** (ONLY university-published email; Tenured Assoc. Prof + Vice Dean) →
+  BEST first contact, the device/integration translator. Senior enough to commit, reachable.
+- **Bin Gao (高滨)** — technical co-target; owns the on-chip update circuitry EP would repurpose (first-author the Sign-Backprop rule).
+- **Huaqiang Wu (吴华强)** — ultimate PI (LEMON lab, http://stor.ime.tsinghua.edu.cn/), hardest to reach cold.
+- Builders: Peng Yao (Nature-2020 CNN, postdoc-level), Wenbin Zhang (STELLAR/Science 2023). Chips: Nature 2020 CNN (HYBRID-
+  trained — only last FC layer in-situ, updates computed in software), STELLAR (Science 2023, full on-chip sign-SGD, 784×100×10
+  MLP), Attar (Sci China Inf Sci 2025 — RRAM transformer but INFERENCE-only). HfOx endurance 10^7 cycles (Nat Electron 2024).
+- ACCESS caveat: top-3-globally, Nature/Science yearly, many suitors + strategic/IP/scope sensitivities. Cold email MUST lead
+  with the specific complementary asset (working EP transformer needing exactly their write-capable substrate → offers them the
+  first local-learning + first in-situ transformer result on their hardware). Warm intro or concrete joint-demo proposal needed.
+- NB for the EP-native map: the agent flagged **Williams–Kumar–Kendall, "Activity-difference training of DNNs using memristor
+  crossbars," Nature Electronics 2023** — an EP-FAMILY (contrastive) rule ON REAL memristor crossbars = a candidate unicorn bridge;
+  and **Grollier (CNRS/Thales), "Training an Ising machine with EP," Nat Commun 2024**. (Confirm in the EP-native synthesis.)
+
+---
+
+## 7. EP-NATIVE complement groups — the "EP-flavored" people (fills the gap EVERY substrate group has)
+The substrate groups (1-6) are EP-poor by design (= our first-mover gap). The EP-native community is a SEPARATE
+world — EP-rich, mostly device-light. Pair one of each.
+- **UPenn physical-learning** (Durian + Andrea Liu faculty; **Dillavou** `dillavou@sas.upenn.edu` hands-on, now part-ARIA;
+  **Menny Stern → own group @ AMOLF Amsterdam**): **Coupled Learning** = EP's experimental sibling, built on real
+  self-adjusting analog circuits (PNAS 2024 "Machine learning without a processor"). The closest real-hardware analog to our method.
+- **Benjamin Scellier** (EP CO-INVENTOR; now **Rain / Rain AI UK**, ARIA-funded; `benjamin@rain.ai`, bscellier.github.io):
+  source authority on EP estimators + energy-based formulations = squarely our AEP/holomorphic domain. HIGH (industry posture).
+- **Axel Laborieux** (→ **Huawei Zurich**; laborieux-axel.github.io) + **Friedemann Zenke** (FMI Basel, senior gateway):
+  co-invented BOTH holomorphic EP (NeurIPS 2022) AND asymmetric EP / Jacobian homeostasis (ICLR 2024) — **literally the two
+  ingredients we build on.** THE algorithm-theory complement. + Maxence Ernoult (→ DeepMind), the estimator-bias-scaling track.
+- **Dmitry Krotov** (MIT-IBM): the **Energy Transformer** (NeurIPS 2023) IS our forward model (energy→fixed-point attention) —
+  trained by autodiff; "train it without backprop" is exactly our EP contribution. HIGH theory complement, no hardware.
+
+## 8. UNICORNS — EP-native AND real updatable device (the rare bridges)
+- **Julie Grollier** (CNRS, **Laboratoire Albert Fert**, Paris-Saclay; neurophysics.cnrs-thales.fr): **ran EP on PHYSICAL
+  hardware** — "Training an Ising machine with EP," Nat Commun 2024 (D-Wave); spintronic-native. The cleanest unicorn: EP-on-
+  hardware experience + device substrate. **Single best EP-native complement.**
+- **Yi / Kendall / Williams / Kumar** — "Activity-difference training of DNNs using memristor crossbars," **Nature Electronics
+  2023**: contrastive two-phase (EP-flavored) training executed on a **fabricated 64×64 RRAM chip** = the closest "EP-on-silicon"
+  that exists, and it overlaps our RRAM/CIM world. Suhas Kumar @ **Sandia**, R. Stanley Williams @ **Texas A&M**, Kendall @ Rain.
+- **Damien Querlioz** (CNRS, **C2N** Paris-Saclay; `damien.querlioz@c2n.upsaclay.fr`): EP-algorithm-native + a real RRAM fab
+  pipeline (CEA-Leti / Elisa Vianello) — near-unicorn (his fabricated learning demos are Bayesian, not yet EP). **Most credible
+  Western partner to actually FABRICATE EP on a crossbar.**
+- ⇒ **Université Paris-Saclay (Grollier + Querlioz, who co-author) = the global EP-on-hardware cluster.**
+- Also EP+device-intent (sim-now): Talatchian/Peters (SPINTEC Grenoble, EP-under-analog-noise), Alex Gower (Cambridge/Nokia,
+  EP on oscillator Ising machines), Kaushik Roy/Sumeet Gupta (Purdue — EP algo + CIM/spintronic devices, not yet fused).
+- NOT EP (don't chase): IBM (Ambrogio/Burr/Sebastian, PCM backprop), Ielmini/PoliMi, McMahon/Wright (physics-aware backprop,
+  not EP), Marquardt (Hamiltonian echo). Rain AI the COMPANY = distressed/acquihire-pending → engage Kendall as an individual.
+
+## REVISED pairing recommendation (the answer to "not EP-flavored")
+- **Lead EP-native = Grollier** (unicorn) × a crossbar substrate (**Tsinghua-Wu/Gao** most mature, **Wong/Raina** most reachable).
+- **Western fab route = Querlioz + Vianello (CEA-Leti)** × **Wenjuan Zhu** — both real updatable-device fabs; Querlioz brings EP fluency.
+- **Algorithm de-risk layer = Laborieux/Zenke** — own the holo + asymmetric-EP bias theory that decides if EP survives analog noise
+  on ANY substrate. **Shanbhag** pairs best here as the systems/CIM error-tolerance partner (his expertise), not the device fab.
+- **High-value individual outreach: Scellier** + the **Kumar/Kendall activity-difference team** (your proof contrastive-equilibrium
+  training already runs on a real memristor chip).
+
+---
+
+## Recommended sequencing
+1. **Shanbhag trio first** (Hwang+Kavishwar, cc Shanbhag; mention Sundaresha) — home dept, closest substrate, richest bench.
+   Consider a Zhai-brokered/in-person intro instead of cold email (same department = warmest path).
+2. **Parallel UIUC PI-direct**: Wenjuan Zhu (device, "extend your FeFETs") + Hanumolu (glue, "point me to a converter student").
+3. **Mingu Kang (UCSD)** — peer-faculty email for the in-situ-update expertise specifically.
+4. **Stanford warm intro** (Jeffrey Yu) via your student — Phase 2.
+5. **THU** — only if/when a connection exists; else cite as the substrate precedent, not a near-term collaborator.
+
+---
+
+## ⏸ STATUS (2026-06-21): HOLD — DO NOT SEND until the 33M demo + scaling dossier
+**User decision (CONFIRMED 2026-06-21): outreach is gated on the ~33M "能看" demo + scaling-law dossier (task #15) — NOT the
+C512/2.09 milestone.** Send nothing until there's a readable-generation ("能看") demo + a scaling-law dossier to lead with.
+(C512 EP descending past the 2.09 wall toward ~1.8 is a prerequisite step that validates the recipe, NOT the outreach gate —
+the gate is the bigger, showable 33M artifact.) Until then: no contact with anyone above.
+When the bar is met: set sender title, render COLLABORATOR_BRIEF.pdf, attach + ept_method_intro.pdf, optionally ask Prof. Zhai
+for a warm intro to Shanbhag/Hanumolu first. All profiles/contacts/pairing/drafts above are durable and ready.
+
+## Email drafts (READY, gated — copy-paste when the bar is met)
+
+### Draft 1 — Shanbhag group · To: Soonha Hwang (soonhah2@), Mihir Kavishwar (mihirvk2@) · cc: Shanbhag
+Subject: Backprop-free (Equilibrium-Propagation) transformer training — a fit for your in-memory CIM work?
+
+Hi Soonha and Mihir,
+
+I'm Yuren Hao, working on backprop-free training in ChengXiang Zhai's group at UIUC. We've gotten Equilibrium Propagation (EP)
+to train a transformer as a physical equilibrium system: the forward pass is a damped relaxation that settles to a fixed point,
+and the weight update is local — computed from a free vs. a nudged settle, no backpropagation. In simulation the EP gradient
+matches backprop (cosine ≈ 1) and comes within a small gap of a same-parameter backprop-trained transformer.
+
+Your DiT memory-in-compute accelerator — and Mihir's compute-SNR-optimal ADC work — is the closest existing substrate I've
+found to what this needs: analog MVM + a settling loop. The one new ingredient is EP's in-situ local weight update, which is
+actually a simpler thing to put on a crossbar than on-chip backprop.
+
+Could I grab 20 minutes to explore whether a small demo — one equilibrium-transformer block on a CIM substrate + our EP control
+loop — is feasible? A one-page overview and short method note are attached. (cc'ing Prof. Shanbhag.)
+
+Thanks, Yuren
+
+### Draft 2 — Wenjuan Zhu · To: wjzhu@illinois.edu (PI-direct)
+Subject: Extending your vdW / CuInP₂S₆ FeFETs to in-situ-trainable analog weights?
+
+Dear Prof. Zhu,
+
+I'm Yuren Hao, working on backprop-free training in ChengXiang Zhai's group at UIUC. We train a transformer as a physical
+equilibrium system using Equilibrium Propagation — no backprop — where learning is a local update from two settled states, and
+the key hardware need is an analog weight whose conductance can be updated in-situ during training.
+
+Your group's vdW / CuInP₂S₆ ferroelectric reconfigurable devices — nonvolatile, electrically programmable, multilevel
+conductance — look like a strong fit for exactly that role. I realize that work has centered on memory and logic rather than
+training, so I'd be keen to explore whether those devices could serve as in-situ-trainable analog synapses for an EP-trained network.
+
+Would you have 20 minutes for me to share what we have (a working EP-transformer in simulation + an analog-noise model) and
+discuss feasibility? One-page overview and a method note attached.
+
+Best, Yuren
+
+### Draft 3 — Hanumolu · To: hanumolu@illinois.edu (PI-direct, ask to route)
+Subject: Mixed-signal converter / control-loop partner for an analog EP-training demo?
+
+Dear Prof. Hanumolu,
+
+I'm Yuren Hao, working on backprop-free training in ChengXiang Zhai's group at UIUC. We're building toward an analog hardware
+demo of Equilibrium Propagation — training a transformer as a physical equilibrium system, where the forward pass is an analog
+settling loop and the weight update is local (no backprop).
+
+Beyond the in-memory compute array, this needs a mixed-signal layer your group is ideally suited for: fast ADC/DAC to read the
+settled state and apply a small "nudge," and switched-cap integrators for the relaxation/control loop. Since that's converter /
+feedback-loop expertise rather than the ML side, could you point me to a student who might be interested — or spare 15 minutes
+to discuss?
+
+A one-pager and method note are attached. Best, Yuren
+
+### Title TODO (all drafts): set Yuren's title ("PhD student" / "researcher") before sending.