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diff --git a/hw_sim/NOTES.md b/hw_sim/NOTES.md index bb616f5..ed5bd75 100644 --- a/hw_sim/NOTES.md +++ b/hw_sim/NOTES.md @@ -32,3 +32,17 @@ Candidate fixes to put to the experts, in our preference order: (c) accept 3.14 us (5% schedule slip). None of this blocks the sim line: v1.1 (mismatch MC / ENOB, noise integration) and stage C (SPICE-in-the-loop toy training) proceed independently of which fix wins. + +## v1.1 (cell_v11.py, 2026-07-17): ENOB Monte Carlo + noise budget +A. Per-BIT ladder mismatch MC (sigma_bit 0.4% ~ datasheet +-1 LSB class), per-cell single-scale + cal: **ENOB 8.51 b mean, p5 8.34 b — clears the 7.0 screen bar with margin.** The Y3 gray- + market screen is realistic. (First model iteration with Thevenin-only structure was vacuous — + single-scale cal cancelled it exactly; per-bit structure is the honest model.) +B. Noise budget at (R_f=1k, C_f=294pF): op-amp 8.7 nV/rtHz x noise-gain peak x16 over the + closed-loop band -> **138.7 uV RMS output-referred vs the 0.1 mV contrast floor = 0.7x + headroom, MARGINAL.** This is hardware wall-1 with a SPICE number: the contrast signal + scales with beta while this floor is fixed -> the machine WANTS big nudges — exactly what + the GPU campaign independently concluded (ride-high beta recipes). Mitigations if more + headroom needed: post-settle integration window (1/sqrt(T)), read averaging, band-limit + after settle, larger VREF. Model caveats: flat op-amp noise only (no 1/f, no Johnson/DAC + switch terms — order-checked small at this impedance level). |