| Age | Commit message (Expand) | Author |
|---|---|---|
| 2026-07-18 | Noise fix quantified (2us window = 3.2x headroom at 1.3x schedule) + JLC boar... | Yuren Hao |
| 2026-07-18 | Fix: Sam Dillavou is one person (UPenn), not two collaborators | Yuren Hao |
| 2026-07-18 | Fab strategy: JLC SMT + socketed screened MDACs + DFT layout + first-article ... | Yuren Hao |
| 2026-07-17 | Energy ledger: SPICE core 2.87pJ/MAC; boards lose ~1000x (trainability demos)... | Yuren Hao |
| 2026-07-17 | Stage C: SPICE-in-the-loop training — SPICE == behavioral == ideal (0.0213/... | Yuren Hao |
| 2026-07-17 | hw_sim v1.1: ENOB-after-cal 8.51b (clears 7.0 bar; per-bit mismatch model) + ... | Yuren Hao |
| 2026-07-17 | hw_sim: bus-settle fix menu parked as Dillavou session question (incl user's ... | Yuren Hao |
| 2026-07-17 | hw_sim v1: datasheet-anchored column — C_bus=5.4nF kills naive design (16.6... | Yuren Hao |
| 2026-07-17 | hw_sim: circuit-as-code workflow stood up (PySpice/ngspice/skidl); cell_v0 â€... | Yuren Hao |
