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# T64 procurement sheet — gray-market MDAC line (v1, 2026-07-16)
Anchor prices: TLC7528CDW (TI, new) $5.05@1k DigiKey, 845 in stock, 9-wk lead.
AD7528JN (ADI, pin-compatible original): UTSource used $0.68–0.72; **Taobao/华强北 spot ¥3/pc
(~$0.42) — user-verified 2026-07-16.** At ¥3 the whole 2,250-cell line is ≈$950; buy 2× and
screen down.
## Phase 1 — screening batch (order NOW, ~¥300–600 total)
- 50–100 pcs × 2–3 DIFFERENT sellers (diversify counterfeit/batch risk). Keep seller lots separated
and labeled — per-lot pass rates decide where the volume order goes.
- Prefer sellers listing date codes / original reels or tubes; DIP (JN) package is fine for the
screening rig; note the volume build may want SOIC (AD7528JR / AD7628KR alternate footprint —
qualify both on the probe PCB).
- Red flags: freshly-blacktopped tops, inconsistent pin-1 markers within a lot, one price far
below the ¥3 street level.
## Phase 2 — acceptance screen (Stage-1 single-column rig doubles as ATE)
Per-part functional screen, in order of kill power:
1. Basic DAC function: full-scale + zero code on both channels; reject hard failures.
2. System settle with 64-load column: **commit ≤3 µs; kill >7 µs** (pre-registered T64 gate).
3. ENOB after per-cell digital pre-scale calibration, 1-hr drift window: **≥7.0** — RELAX this bar per the Stage-0 qcomp verdict (gate #1b, compute-quantization = the T64 scenario).
Gate #1 (naked resident updates) measured: 10b +0.012 / 8b +0.042 / 6b +0.092 vs ctl — irrelevant
to T64 (fp32 master lives in DDR) but rules out shadow-less resident-cell machines below 10 bits.
4. Channel gain mismatch / INL spot-check at 4 codes (0x40/0x80/0xC0/0xFF): within the
forward/transpose asymmetry budget from Stage-0 gate #2 (pending).
Log pass-rate per seller lot; ≥70% pass at the relaxed bar makes the ¥3 line the plan of record.
## Phase 3 — volume buy (after G1 + qup verdicts)
- 2,250 required + overage sized by measured pass-rate (default 2× at ¥3 ≈ ¥13.5k ≈ $1.9k).
- Fallback capped: TI TLC7528CDW new ($11.4k line) stays available (ACTIVE) — worst case 8×
price, zero schedule risk.
- Customs/compliance: 1980s commodity DACs, no export-control exposure; UTSource invoices work
for university reimbursement, Taobao spot = personal advance.
## Do NOT spend effort on
Chopper choice, FRAM vs SRAM, PCB vendor substitutions — audited ≤2–3× movers. The money is in
this MDAC line (8–12×) and consumer-grade converter periphery (PCM1808 $0.90/ch ADC,
TLC5947 $0.17/ch DAC, 10–30× vs instrumentation-grade).
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