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+# Digital coupled-learning scaling protocol
+
+## Paper role
+
+The paper has three experimental parts.
+
+1. **Digital plug-in transfer.** Add the same local SDIL residual to the
+ existing digital local-learning backbones and measure recovery from a
+ matched teaching-channel imperfection.
+2. **Digital coupled-learning scaling.** Isolate system size in a sparse
+ coupled-learning lattice. Compare ideal learning, fixed component
+ imperfection, same-RMS zero-mean noise, and SDIL under paired tasks and
+ component draws.
+3. **Hardware-realistic simulation.** Use the reconstructed nonlinear CLLN,
+ the Appendix-C component model, and the nonideal CDS/autozero primitive.
+
+Part 2 tests the scaling mechanism cheaply. Part 3 tests whether the local
+operation survives the constraints of the proposed hardware substrate.
+
+## Frozen ladder
+
+- Topology: periodic square resistor grid.
+- Side lengths: `4, 8, 12, 16, 24, 32`.
+- Learnable edges: `2 * side^2`, from 32 to 2,048.
+- Boundary geometry: the released 4-by-4 source and target layout scaled with
+ the grid side. The side-4 circuit is exactly the released layout.
+- Task family: the 40 released Figure-5 ring-classification tasks: five input
+ diameters and eight label rotations.
+- Initial state: tile each released 4-by-4 gate pattern over the larger grid.
+- Pairing: every method receives the same task, initial gates, and component
+ draw. Component draws are nested within task and size.
+- Size-dependent optimization: select the learning exposure using ideal
+ coupled learning only, then freeze it for every imperfect condition at that
+ size.
+
+## Conditions
+
+| Condition | Local teaching measurement |
+|:--|:--|
+| clean | ideal voltage-square difference |
+| matched noise | ideal update plus a fresh random-sign version of the measured imperfection |
+| raw bias | fixed per-edge gain, input-offset, and multiplier-offset errors |
+| SDIL | raw task-period measurement minus the same edge's instruction-off measurement |
+| constant calibration | raw measurement minus a frozen per-edge mean, used as a bias-specific baseline |
+| overclamping | the published stronger-clamp correction, used after the core ladder is stable |
+
+The SDIL subtraction reads local voltage drops and the local learning channel.
+It does not read a device constant, a task loss, a downstream weight, or a BP
+gradient. Every neutral observation and local scalar is counted.
+
+## Primary endpoints
+
+Accuracy remains the task endpoint. Predictor error and update residuals are
+diagnostics.
+
+- final classification error at a matched epoch budget;
+- fraction of task/device pairs reaching zero classification error;
+- restricted epochs and local updates to zero error, assigning the experiment
+ horizon to runs that do not reach the target;
+- learning-curve area for classification error;
+- wall time and neutral observations as implementation costs.
+
+For each endpoint, plot task-clustered means and 95% paired bootstrap
+intervals. Device draws are averaged within each task before resampling tasks.
+
+## Scaling statement
+
+Fit each predeclared endpoint against learnable edge count on log axes. Report
+the two method slopes, their paired bootstrap interval, and the relative slope
+change. The headline wording is selected from the observed sign:
+
+- lower resource exponent: “SDIL reduces the updates-to-target scaling
+ exponent by X%”;
+- lower error-growth exponent: “SDIL reduces imperfection-induced error growth
+ with network size by X%”;
+- overlapping interval: report no resolved scaling-rate difference.
+
+The plots may use the visual organization of Figure 4 in arXiv:2507.02092,
+but every axis is an independent experimental intervention or a separately
+named endpoint. Nodes, edges, and FLOPs from the same ladder are not presented
+as independent confirmations.
+
+## Gates
+
+1. The side-4 linear circuit reproduces clean task learning.
+2. Clean learning remains viable across the ladder after clean-only exposure
+ selection.
+3. Fixed imperfection is worse than the same-RMS zero-mean control on at least
+ one task endpoint.
+4. SDIL improves raw biased learning at every reported size and retains its
+ advantage at the two largest sizes.
+5. The scaling conclusion is computed from all frozen sizes and task clusters,
+ including failed runs.
+6. Hardware-realistic claims use Part 3 only.
+