Hardware outreach v2: gate lifted, clockless-MVP story, Dillavou wave-1, brief rewritten to cascade-era

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_014FAPDWQ49M5Ye3NpTndTpn

3 files changed, 195 insertions, 42 deletions

diff --git a/docs/hardware/COLLABORATOR_BRIEF.md b/docs/hardware/COLLABORATOR_BRIEF.md
index 3728657..0ce68ea 100644
--- a/docs/hardware/COLLABORATOR_BRIEF.md
+++ b/docs/hardware/COLLABORATOR_BRIEF.md
@@ -1,46 +1,57 @@
-# Backprop-free analog training of a transformer — collaboration brief
-**One-page ask for hardware-side collaborators · 2026-06-21 · Yuren Hao (UIUC)**
+# Backprop-free training of transformers — results and a staged hardware program
+**One-page brief for hardware-side collaborators · rev. 2026-07-12 · Yuren Hao (UIUC)**
 
 ## The idea in three sentences
-We train a **transformer block as a physical equilibrium (fixed-point) system** using **Equilibrium Propagation
-(EP)** — no backpropagation. The forward pass is a damped relaxation `z ← z + ε·F(z)` that **settles** to a fixed
-point (on analog hardware, the settling *is* the physics — nearly free); the weight update is **local**, computed
-from the contrast between a free settle and a slightly-nudged settle. This is exactly the computation an analog
-in-memory / memristive array is good at — and unlike every shipping analog-AI chip (all inference-only), it needs
-**in-situ weight update**, which is the open opportunity.
+We train **standard multi-layer transformers** with **Equilibrium Propagation** on a layered energy:
+training consists of two relaxation phases and a **local** contrast update per weight — no
+backpropagation anywhere — and inference is an ordinary forward pass. On GPU this now works at
+language-model scale with essentially no quality gap to backprop. The hardware program starts with
+the cheapest object that can validate the physical learning rule — a **clockless twin-network
+analog tile (~$300)** — and climbs rung by rung to an in-memory-compute transformer block.
 
-## Why now / why it's real (not speculative)
-- **Algorithm side (ours, in simulation):** EP's gradient matches true backprop (cosine ≈ 0.99–1.0 per component);
-  the equilibrium transformer trains stably and **matches/beats a same-parameter BP transformer** on language modeling.
-  Currently scaling the recipe; a fix for the one known instability (a residual-defense term) is under validation.
-- **Hardware precedent exists:** local contrastive/EP learning has been physically demonstrated (self-learning analog
-  resistor networks, ~1 µs settling, on-chip weight update from a local free-vs-clamped difference; EP on a D-Wave
-  Ising machine). **But nobody has built an EP-trained *transformer* in analog hardware — that is the first-mover demo.**
-- **Endurance clears the bar:** HfOx-class RRAM survives ~10^10 write cycles; a training run needs ≤10^8 device writes
-  (fewer with digital-accumulate-then-threshold-program). Endurance is not the blocker — update linearity/symmetry is
-  the real device challenge.
+## GPU-scale results (2026-07, measured)
+- **A 12-layer, 42.7M-parameter transformer LM trained for a full epoch (59k steps, 361M tokens)
+  with no backpropagation in the training loop; it generates coherent text.** To our knowledge the
+  first transformer language model trained fully this way.
+- **Gap to a tuned, same-architecture backprop control: 0.05 nats** (at 4k steps: statistically
+  indistinguishable, 3 seeds/arm). Prior backprop-free attempts at scale all report qualitative gaps.
+- EP step = **3.2× backprop FLOPs** (measured); mixed-precision training validated; the two known
+  EP-specific instabilities are mechanistically diagnosed and closed (an estimator-SNR floor with a
+  β-schedule law; a relaxation-contractivity crossing eliminated by norm placement).
+- **Every trained operation chosen analog-implementable:** crossbar MVM, divisive normalization,
+  fixed I/Q rotations (position code), translinear gated MLP, subthreshold-exponential softmax,
+  two-phase relaxation for the learning rule.
 
-## What a hardware demo needs (three layers) — and the UIUC ECE fit
-| Layer | What it does | Closest collaborator |
-|---|---|---|
-| **Trainable device** | in-situ-updatable analog weights (RRAM/FeFET/ECRAM) — *the part you cannot buy* | **Wenjuan Zhu** (UIUC ECE, memristor/RRAM/FeFET/2D devices) |
-| **In-memory MVM circuit** | analog matrix-vector multiply + on-chip weight write-back | **Naresh Shanbhag** (UIUC ECE) — his JSSC-2018 DIMA chip *already* does analog MVM **+ on-chip SGD weight write-back** in 65nm; nearest existing substrate |
-| **Mixed-signal glue / control loop** | ADC/DAC to read settled states + apply the nudge; switched-cap integrators = relaxation primitives | **Pavan Hanumolu** (UIUC ECE, data converters / PLL / switched-cap) |
-| **EP control + sim** | the settle→nudge→settle→local-Δθ loop, noise/endurance de-risk in simulation | **us** (FPGA + the trained model + analog-noise sim already built) |
+## Measured fault tolerances (fault injection at the trained model)
+| fault | free | marginal | dead |
+|---|---|---|---|
+| weight precision | **8-bit** (ΔCE +0.004) | 6-bit (+0.05) | 4-bit |
+| forward state noise | **1%** | — | — |
+| error-channel (nudge) noise | **10% relative** | 30% | — |
+| divider mismatch / gate gain / phase error | 3% / 10% / 0.03 rad | 10% / — / 0.1 rad | — |
 
-**Escalation / device frontier:** **H.-S. Philip Wong (黄汉森, Stanford EE / TSMC Chief Scientist)** — NeuRRAM (Nature
-2022) is the most EP-relevant analog-MVM substrate (inference-only today); the RRAM-device heavyweight + a TSMC-foundry
-path, reachable via a Stanford student contact.
+Under every non-fatal fault the learning signal tracks the *faulted* network (gradient cosine ≈ 0.97
+invariant): **the rule co-adapts to the device.** The only hard spec is ~7-bit effective weights.
 
-## The concrete ask (staged, modular — stitch existing capabilities, no startup-scale custom fab)
-- **Phase 1:** put ONE equilibrium-transformer block on an existing in-situ-trainable substrate (Shanbhag's DIMA-class
-  chip + Hanumolu converter/integrator glue; Zhu devices) + our FPGA EP-control loop → prove end-to-end analog EP training.
-- **Phase 2:** scale weights (foundry RRAM MPW — e.g. SkyWater S130 + Weebit ReRAM IP — or a fixed-weight inference array
-  for the forward path with the trainable layer in-situ).
-- **What we bring:** the validated algorithm, the trained model + scaling data, the EP control logic, and a simulator
-  that already models analog non-idealities (device noise / quantization / asymmetric update) to de-risk before tape-out.
+## The hardware ladder (each rung publishable alone)
+1. **One-edge metrology tile ($70–130):** twin MOSFET edge, shared weight capacitor, exact
+   (difference-of-squares) and sign-only local update channels, OTA current nudge — no processor,
+   converter, clock, or sampled memory in the learning loop.
+2. **8-edge twin network ($170–300):** nonlinear regression; EP current-nudge vs Coupled-Learning
+   voltage-clamp on one board; exact-vs-sign update comparison; measured bias-vs-nudge-magnitude
+   curve (the same β-SNR law we measured in simulation).
+3. **32-edge network ($450–900):** replication-class nonlinear tasks, robustness study.
+4. **Reciprocal attention microcell (+$100–250):** two tokens, one head, energy-based attention.
+5. **CIM transformer block (partner phase):** analog MVM + in-situ two-phase EP weight update —
+   the piece no shipping analog-AI chip has (all are inference-only or on-chip-backprop).
+6. **North star: a few-M-parameter TinyStories LM trained on analog hardware.**
 
-**Bottom line:** the science is done in sim and the hardware pieces all exist in-house at UIUC ECE — this is a
-stitching + first-demo opportunity, not a multi-year custom-silicon program.
+## What we bring / what we ask
+**Bring:** the trained models and recipe, the estimator theory (β-SNR law, stability walls), the
+measured tolerance ledger, SPICE-first costed build plan, and parts funding (rungs 1–3 are <$1k).
+**Ask (rungs 1–3):** bench access, analog-design mentorship, and/or a student who enjoys discrete
+analog — six-week plan, instruments = a scope and a DMM. **Ask (rung 5):** a CIM/mixed-signal
+partnership where the substrate expertise is yours and the learning rule is ours.
 
-*(Backing detail + citations: HW_RESEARCH_FINDINGS.md; method: ept_method_intro.pdf)*
+*(Detail: CLOCKLESS_ANALOG_MVP_PLAN.md — full BOM, schedule, acceptance criteria, claim limits;
+COMPONENT_HW_MAP.md — per-operation analog mapping + tolerance status.)*
diff --git a/docs/hardware/COMPONENT_HW_MAP.md b/docs/hardware/COMPONENT_HW_MAP.md
index ff47123..0cae1ea 100644
--- a/docs/hardware/COMPONENT_HW_MAP.md
+++ b/docs/hardware/COMPONENT_HW_MAP.md
@@ -48,7 +48,12 @@ Companion docs: `HW_RESEARCH_FINDINGS.md` (softmax dossier, OLMo2 analog audit,
 
 ## D. Demo scoping (reuse-doctrine currency)
 
-- **Demo-0 (spec target of E-tier):** single cascade block, SRAM-CIM eval module + FPGA harness +
+- **⚡ 2026-07-12: Demo-0 SUPERSEDED as the first rung by CLOCKLESS_ANALOG_MVP_PLAN.md**
+  (user-authored): a $170–300 clockless twin-network tile (Dillavou-lineage; EP current-nudge vs CL
+  voltage-clamp; exact vs sign local update; no processor/converter/clock in the learning loop)
+  validates the physical learning primitive first. The CIM block below becomes the PARTNER rung
+  (rung 5 of the ladder in COLLABORATOR_BRIEF.md).
+- **Demo-0 (now rung 5, partner phase):** single cascade block, SRAM-CIM eval module + FPGA harness +
   COTS mixer/DAC/ADC periphery; goal = demonstrate the two-phase θ-read on one block with measured
   tolerances. Board-BOM class: $5–20k.
 - **Demo-1:** time-multiplex ONE physical trainable block through L logical positions (cascade's
diff --git a/docs/outreach/OUTREACH_TARGETS.md b/docs/outreach/OUTREACH_TARGETS.md
index ffbd177..e4cfdad 100644
--- a/docs/outreach/OUTREACH_TARGETS.md
+++ b/docs/outreach/OUTREACH_TARGETS.md
@@ -1,4 +1,140 @@
-# EP analog-hardware collaboration — outreach targets (2026-06-21)
+# EP analog-hardware collaboration — outreach targets (2026-06-21; REVISED 2026-07-12)
+
+## ⚡ 2026-07-12 REVISION — gate LIFTED, story changed by the clockless MVP
+**User instruction 2026-07-12: outreach begins now.** Gate artifacts in hand: 42.75M full-epoch
+"能看" demo (first BP-free transformer LM, gap 0.05 nats), E-tier tolerance ledger, cost model,
+and **CLOCKLESS_ANALOG_MVP_PLAN.md** (user-authored) which replaces the $5–20k CIM Demo-0 with a
+**$170–300 clockless twin-network tile** (Dillavou-lineage; EP-current vs CL-voltage on one board;
+exact vs sign local update; no processor/converter/clock in the learning loop).
+
+**What the MVP changes about outreach:**
+1. The ask shrinks from "help us engineer a CIM demonstrator" to "host/advise a $300, six-week,
+   scope-and-DMM bench build" — any analog lab can say yes.
+2. The scientific lineage points at the **physical-learning community (Penn/Dillavou)**, not only
+   CIM-VLSI. Dillavou becomes a wave-1 target (his PNAS 2024 board is the design's ancestor; our
+   deltas: true EP current nudge, exact-vs-sign matrix, the LM program + β-SNR law transfer).
+   Affiliation note (checked 2026-07-12): LinkedIn = "Independent Researcher, ARIA R&D Creator";
+   Penn pages still list postdoc (Durian/Liu). Email the Penn address; keep title-neutral wording.
+3. Substrate groups (Shanbhag CIM, Zhu FeFET, THU, Stanford) are **rung-5 partners** (CIM block) —
+   still first-mover whitespace, pitched as the rung AFTER the tile, which makes us look staged
+   rather than speculative. Hanumolu's converter relevance drops (MVP deletes converters) → wave-2.
+4. Shared quantitative hook everywhere: the board's Factor-4 (bias-vs-nudge-magnitude) = the wall-1
+   β-SNR law we measured in fp32 + the E-tier error-channel result (10% relative noise free) —
+   "the same law, measured in simulation and in physics."
+
+**Revised sequencing:** wave-1a **Dillavou** (design review + natural collaborator; fastest
+credible yes/no) → wave-1b **Shanbhag trio** (local bench + rung-5 CIM; E-tier speaks compute-SNR)
+→ wave-2 Zhu (nonvolatile-weight rung: film cap → FeFET conductance), Hanumolu (rung-5 mixed-signal
+glue), Mingu Kang, Stanford → unicorns (Grollier/Querlioz) once the 32-edge board exists.
+**Ben/Rain thread stays separate** — the MVP plan flows there after the current Overleaf beat.
+
+**Attachments per send:** COLLABORATOR_BRIEF (rev. 2026-07-12, rewritten to cascade-era) +
+CLOCKLESS_ANALOG_MVP_PLAN.md (Dillavou/Shanbhag) — render to PDF and VISUALLY VERIFY before send.
+Sender-title TODO still open. Current drafts: §"Email drafts v2" below; the 2026-06-21 drafts at
+the bottom are SUPERSEDED (looped-era framing, CIM-first ask).
+
+---
+
+## Email drafts v2 (2026-07-12) — copy-paste after title/attachment check
+
+### Draft B (wave-1a) — Sam Dillavou · To: dillavou@sas.upenn.edu
+Subject: A true-EP current nudge on a twin-network learning circuit — building on your PNAS design
+
+Hi Dr. Dillavou,
+
+I'm Yuren Hao (UIUC). Two results may interest you. On the algorithm side, we recently trained a
+standard 12-layer transformer language model entirely without backpropagation — equilibrium
+propagation on a layered energy, all updates local — to within 0.05 nats of a tuned backprop
+control over a full epoch; it generates coherent text. On the hardware side, we are starting a
+physical-learning build whose design descends directly from your processor-free network: two
+continuously-running replicas, shared weight capacitors, local contrast updates, no clock or
+processor in the learning loop.
+
+The planned departures from your architecture are the reason I'm writing. First, an OTA current
+nudge alongside the voltage clamp, so EP's force nudge and Coupled Learning's constraint can be
+compared on the same board — the distinction McGinnis, Li and Mori recently formalized. Second, one
+exact difference-of-squares contrast channel running in parallel with sign-only update cells, for a
+continuous exact-versus-sign comparison. Third, a measured bias-versus-nudge-magnitude curve: in
+simulation we find the EP error channel tolerates 10% relative noise, while an additive precision
+floor sets a hard threshold on the nudge amplitude — the board should exhibit the same law in
+physics, and your imperfection-characterization paper is the closest existing treatment.
+
+Would you have 20–30 minutes to talk? We would value your judgment on the design before we commit
+the board, and there may be a natural collaboration — we bring the transformer/LM program and the
+simulation tolerance data; the physical-learning lineage is yours. A one-page brief and the build
+plan are attached.
+
+Best, Yuren
+
+### Draft A (wave-1b) — Shanbhag group · To: Soonha Hwang (soonhah2@), Mihir Kavishwar (mihirvk2@) · cc: Shanbhag
+Subject: Backprop-free transformer training — GPU-scale results and a staged path to CIM
+
+Hi Soonha and Mihir,
+
+I'm Yuren Hao, working on backprop-free training in ChengXiang Zhai's group at UIUC. The project
+recently crossed a threshold worth reporting: we trained a standard 12-layer transformer language
+model with equilibrium propagation — no backpropagation anywhere in training, every update local —
+to within 0.05 nats of a tuned backprop control over a full epoch, and it generates coherent text.
+Inference is an ordinary forward pass. Every operation in the recipe was chosen to have a known
+analog implementation, and we have measured the fault tolerances the learning rule actually needs:
+8-bit effective weights are lossless and 6-bit marginal; the error channel tolerates 10% relative
+noise; 1% forward state noise costs nothing.
+
+We are deliberately starting the hardware small: a ~$300 clockless twin-network tile (descended
+from the Penn processor-free learning circuits) that validates the physical learning rule with no
+processor, converter, or clock in the loop. The reason to write to your group is the rung after
+that: a CIM transformer block with in-situ EP updates — analog MVM plus a local two-phase weight
+update. Your DiT accelerator and the compute-SNR ADC line are the closest existing substrate for
+that rung, and the tolerance table above is, in effect, its SNR budget.
+
+Could I grab 20 minutes to show the results and the staged plan? A one-page brief is attached.
+(cc'ing Prof. Shanbhag.)
+
+Thanks, Yuren
+
+### Draft C (wave-2) — Wenjuan Zhu · To: wjzhu@illinois.edu
+Subject: Nonvolatile analog weights for a physical equilibrium-propagation learner — FeFET fit?
+
+Dear Prof. Zhu,
+
+I'm Yuren Hao, working on backprop-free training in ChengXiang Zhai's group at UIUC. We train
+transformers with equilibrium propagation — no backpropagation; each weight updates from a local
+contrast between two settled states — and recently demonstrated this at language-model scale in
+simulation (a 12-layer model within 0.05 nats of its backprop control). We are now building a small
+clockless analog learning network in which each weight is a capacitor charged by its own local
+update circuit.
+
+The capacitor is the honest weakness: it is volatile. The natural upgrade is exactly your group's
+territory — a nonvolatile, electrically-programmable, multilevel conductance, and your vdW /
+CuInP2S6 FeFETs are the closest devices I know of. I realize that work has centered on memory and
+logic rather than training; the question is whether a FeFET conductance could replace the weight
+capacitor in a continuously-learning analog network, with the update current driving the gate.
+
+Would you have 20 minutes to discuss feasibility? A one-page brief and the build plan are attached.
+
+Best, Yuren
+
+### Draft D (wave-2) — Hanumolu · To: hanumolu@illinois.edu
+Subject: Mixed-signal partner for the CIM phase of an analog learning program — student pointer?
+
+Dear Prof. Hanumolu,
+
+I'm Yuren Hao, working on backprop-free training in ChengXiang Zhai's group at UIUC. We train
+transformers with equilibrium propagation (no backpropagation; local two-phase updates), recently
+at language-model scale in simulation, and are starting the hardware side with a deliberately
+minimal clockless analog tile — no converters at all in the learning loop.
+
+The phase where your group's expertise becomes central is the one after: an in-memory-compute
+transformer block, where settled-state readout, nudge injection, and loop stability are
+mixed-signal problems. Nearer-term, the tile itself has one control-loop question — enforcing a
+100–1000× time-scale separation between state settling and weight motion — that a student who
+enjoys discrete analog and feedback loops might find fun as a side project.
+
+Could you point me to a student for either, or spare 15 minutes? One-page brief attached.
+
+Best, Yuren
+
+---
 Per-group PhD/PI profiles from 5 research agents. Accuracy discipline: emails only where published or netid on an
 official directory; "—" = not public, route via PI (no invented addresses). Verify "current" status before sending —
 students graduate. Companion: COLLABORATOR_BRIEF.md (the one-pager), HW_RESEARCH_FINDINGS.md (citations).
@@ -133,7 +269,8 @@ world — EP-rich, mostly device-light. Pair one of each.
 
 ---
 
-## ⏸ STATUS (2026-06-21): HOLD — DO NOT SEND until the 33M demo + scaling dossier
+## ~~⏸ STATUS (2026-06-21): HOLD~~ → **GATE LIFTED 2026-07-12 (user instruction; artifacts delivered). Use "Email drafts v2" above; everything below is the superseded 06-21 record.**
+## (superseded) ⏸ STATUS (2026-06-21): HOLD — DO NOT SEND until the 33M demo + scaling dossier
 **User decision (CONFIRMED 2026-06-21): outreach is gated on the ~33M "能看" demo + scaling-law dossier (task #15) — NOT the
 C512/2.09 milestone.** Send nothing until there's a readable-generation ("能看") demo + a scaling-law dossier to lead with.
 (C512 EP descending past the 2.09 wall toward ~1.8 is a prerequisite step that validates the recipe, NOT the outreach gate —
@@ -141,7 +278,7 @@ the gate is the bigger, showable 33M artifact.) Until then: no contact with anyo
 When the bar is met: set sender title, render COLLABORATOR_BRIEF.pdf, attach + ept_method_intro.pdf, optionally ask Prof. Zhai
 for a warm intro to Shanbhag/Hanumolu first. All profiles/contacts/pairing/drafts above are durable and ready.
 
-## Email drafts (READY, gated — copy-paste when the bar is met)
+## Email drafts v1 (2026-06-21) — SUPERSEDED by v2 above (looped-era framing, CIM-first ask; kept for the record)
 
 ### Draft 1 — Shanbhag group · To: Soonha Hwang (soonhah2@), Mihir Kavishwar (mihirvk2@) · cc: Shanbhag
 Subject: Backprop-free (Equilibrium-Propagation) transformer training — a fit for your in-memory CIM work?