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Diffstat (limited to 'results/figs')
| -rw-r--r-- | results/figs/physical_bias_p0.png | bin | 0 -> 264202 bytes | |||
| -rw-r--r-- | results/figs/physical_bias_p0_caption.md | 13 |
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diff --git a/results/figs/physical_bias_p0.png b/results/figs/physical_bias_p0.png Binary files differnew file mode 100644 index 0000000..0d5dbb3 --- /dev/null +++ b/results/figs/physical_bias_p0.png diff --git a/results/figs/physical_bias_p0_caption.md b/results/figs/physical_bias_p0_caption.md new file mode 100644 index 0000000..0e8fe9a --- /dev/null +++ b/results/figs/physical_bias_p0_caption.md @@ -0,0 +1,13 @@ +**Published physical structured-bias reproduction.** All panels are regenerated +from the raw small-network files released by Dillavou et al. in Zenodo record +`15692914` (release `v1.0.1`). **A,** Combined learning error approaches a +nonzero low-period plateau in three physical experiments. Fits to the lowest +six periods have log--log slopes `0.062`, `0.288`, and `-0.024`. **B,** Squared +cycle span grows approximately quadratically with switching period over the +same points (slopes `1.837`, `1.736`, and `1.947`; dashed lines show quadratic +references). **C,** The resulting span-per-period proxy remains finite at +short periods, as expected for deterministic drift that is not removed by +faster alternation. **D,** Released gate-voltage trajectories from physical +experiment 1 show the measured bias-driven cycles. This is a descriptive +reanalysis of published hardware data, not evidence that SDIL corrects the +bias. |
